JPS6052447B2 - Microprogram order control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram order control system that allows a microprogram to perform various branches in a microprogram electronic computer without adding dedicated hardware.

In conventional microprogram electronic computers, when a microinstruction itself gives a branch address BRADR and branches within a microprogram as shown in FIG. 1, a specific field of the microinstruction is transferred from the microinstruction register MIR to the microprogram. The address is directly sent to the address control unit AC that controls the address.

Here, BR represents a branch control signal. Then, the next microinstruction to be executed is specified in the microprogram memory MM via the program counter PC.
Conventionally, the following method has been used to send a specific field of the microinstruction from the microinstruction register MIR to the address control unit AC. In other words, each microinstruction always has a part of it as a branch-only field, and each microinstruction specifies the address of the next microprogram to be executed.

Alternatively, since microprograms are usually executed sequentially, the execution address of the microprogram is specified using a program counter PC, and updated every time one microinstruction is executed.
This is a system in which a specific field of a microinstruction is given as a branch address to the address control unit AC together with a branch condition only when a branch is executed. However, in such a system, since the branch address is directly sent to the address control unit AC, the value of the address is fixed, and there is a drawback that the destination address cannot be changed depending on the processing result of the program.

The present invention handles branch addresses in microprograms in exactly the same way as data operations, and by performing operations on branch addresses, it is possible to perform various branches in microprograms without adding dedicated hardware. The purpose is to provide a program order control method that does not have any drawbacks.

The present invention will be explained below with reference to the drawings.

FIG. 2 shows an embodiment of the present invention, in which:
The specific field of the microinstruction is transferred to the data bus BUSl.
2, and the output of the arithmetic unit, ALU, is connected to the address control unit AC via a data output bus BUS2. Normally, when microprograms are executed sequentially, the contents of the program counter PC are updated, and the microinstructions read from the microprogram memory MM according to the value of the program counter PC are set in the microinstruction register MIR. Ru.

The output of this microinstruction register MIR is decoded as necessary, and a portion of it is also allocated to the arithmetic units AL and U. When a microinstruction specifies a branch, the arithmetic unit Al. The input of U selects the value of the branch field of the microinstruction register MIR via the data input bus BUS12.

As a result, the calculation unit ALU performs calculation of the branch address value in the same way as normal data calculation.

The value input to the arithmetic unit ALU is directly applied to the address control unit AC via the data output bus BUS2, and is branched to the address specified by the branch field of the microinstruction. Furthermore, if a register or the like is connected to the data input bus BUSll, it becomes possible to perform an operation between the data input bus BUSll and the data input bus BUSl2 to which a branch address is given.

The data source to be applied to the data input bus BUSll and the calculation to be performed in the calculation unit ALU are specified by the microphone command register M.
Controlled by microinstructions held in the IR.
For example, when branching to a different address depending on the contents of the status register FLR consisting of several bits, the contents of the status register FLR are given to the data input bus BUSll, the branch address is given to the data input bus BUS12, and the arithmetic section Al. Enter into U. The arithmetic unit ALU adds two pieces of data and sends the result to the address control unit AC. Thereby, it is possible to branch to one address among a plurality of addresses according to the contents of the status register JFLR with one microinstruction. Also, the interrupt control unit 1CU is connected to the data input bus BUSll. As a result, when an interrupt occurs, the interrupt level of the interrupt control unit 1CU of the interrupt processing microprogram is set to the data input bus BU.
The signal is input to the arithmetic unit ALU via the Sll. Arithmetic unit ALU
performs operations such as addition from this input value and the value of the branch field of the microinstruction, sends the result to the address control unit AC, and branches the microprogram to a specific address according to the interrupt factor. In order to implement subroutine functions using microprograms, special circuits had to be added.

However, in the present invention, this can be easily realized and the return can be performed in various ways. That is, FIG. 3 shows another embodiment of the present invention, in which the subroutine is called as follows. In the figure, RF represents a register file having a plurality of registers therein, and N/10R represents a return address. First, the return address from the subroutine, that is, the next address of the microinstruction that calls the subroutine, is sent from the address control unit AC to the data input bus BUSll, and this is sent to the arithmetic unit, AL. Execute the microphone command to be stored in the register file RF via U. At this time, if the microinstruction is made to save the status at the same time, the value of the status register FLR is sent to the data input bus BUSll together with the value of the return address, and is saved in the register file RF together with the status when the subroutine is called. Next, a subroutine call instruction is executed. This transfers the branch address created by the branch field of the microinstruction to the data input bus BUS12 and the arithmetic unit AL. It is sent to the address control unit AC via U. FIG. 4 shows the data format at this time. Further, when returning from the subroutine, the contents of the register file RF in which the return address is stored are read out and calculated by the calculation unit ALU. and data output bus BU
A microinstruction sent to the address control unit AC via S2 is executed. If the operation in the arithmetic unit or ALU is a transfer operation, the stored return address will be sent out as is and will return to the next microinstruction that called the subroutine, but if an operation such as addition is performed, the return address will be changed. can be freely controlled. Therefore, this method is effective when it is desired to change the return address depending on the result of subroutine processing. At this time, if you make a microinstruction that also returns the status, the status register FLR will be sent via the data output bus BUS2.
The original status is sent to Although two microcommands are required to call the sublunitine described above, another embodiment of the present invention in which this can be performed with one microinstruction will be described next.

In FIG. 5, first, the branch address of the microinstruction register MIR is stored in advance in one register of the register file RF via the arithmetic unit ALU and the internal data bus BUS32. When a microinstruction that calls a subroutine is executed, the return address is sent to data input bus B.
It is sent to USll and stored in the register of the register file RF via the arithmetic unit ALU and internal data bus BUS32. At the same time, the branch address of the subroutine stored in advance is transferred to the internal data bus BUS3l.
and the data output bus BUS via the multiplexer MPX.
Output to 2. This data is sent to the address control section AC. In this case, one register in the register file RF must be reserved for storing the branch address of the subroutine. Next, an embodiment that does not require this register will be described.

In FIG. 6, when a microinstruction calling a subroutine is executed, a return address is sent from the address control unit AC to the data input bus BUSll, and is stored in the register file RF via the multiplexer MPX. At the same time, the value of the branch field of the microphone instruction register MIR is output to the data input bus BUS12 via the data input bus BUS12 and the arithmetic unit ALU. This data is sent to the address control section AC. In this method, the contents of the program counter PC and the status register FLR are stored in advance in a register file RF. When returning from the subroutine, the calculation unit AL. The return address in D is characterized in that the return address can be changed freely by performing appropriate calculations and sending this data to the address control section AC and the status register FLR. In this way, the microprogram order control method of the present invention calculates branch addresses in the calculation unit ALU in exactly the same way as data, and when it is necessary to save this data, stores it in an arbitrary register of the register file RF. . When performing a branch, the branch address created by the data stored in the register file RF or a specific field of the microinstruction is sent to the arithmetic unit Al. It is calculated by U and then sent to address control unit AC and status register Hλ. Therefore, microprograms can be branched in a variety of ways with a simple circuit configuration, making it possible to assemble efficient microprograms and improve program execution speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a program order control unit in a conventional microprogram control system electronic computer, FIG. 2 is a block diagram showing an embodiment of the configuration of the microprogram order control unit according to the present invention, and FIG. 4 is a block diagram showing another embodiment of the present invention, FIG. 4 is a data format of the present invention, FIG. 4A is a format diagram of an unconditional branch instruction, and FIG. , 5 and 6 are block diagrams showing other embodiments of the present invention. AC: Address control unit, MM: Micro program memory, MIR: Micro instruction register, ALU: Arithmetic unit, BR: Branch control signal, BR, ADR...Branch address, NADR゜゜return address, PC...
Program counter, bow CU...Interrupt control unit, BUSll, BUSl2...data input bus, BU
S2...Data output bus, FLR...
Status register, RF... Rujista file, MP
X...Multiplexer, BUS3l, BUS3
2...Internal data bus.

Claims (1)

[Claims] 1. An address control unit that specifies an execution address of a microprogram of a microprogram control computer;
A predetermined operation is performed in accordance with the microinstruction in a microprogram order control unit consisting of a microprogram storage unit that reads the microinstruction based on the output signal of the address control unit, and a microinstruction register that holds the read out microinstruction. It is provided with an arithmetic unit, a status register determined by the arithmetic result of the arithmetic unit, a register file consisting of a plurality of registers and for storing data, and an interrupt control unit that controls interrupts, and includes a part of the microinstruction or A value read from the register file is sent to the address control unit via the calculation unit, or a part of the microinstruction and the value of the status register or the value of the interrupt control unit are input to the calculation unit as calculation data. A microprogram order control system characterized in that the microinstruction controls a function of performing an addition or a logical OR operation and then sending the output of the operation to the address control section. 2. The microprogram order control system according to claim 1, wherein a function of sending a value read from the address control section to the register file via the calculation section is controlled by the microinstruction.