JPS6052056A - Semiconductor thyristor - Google Patents
Semiconductor thyristorInfo
- Publication number
- JPS6052056A JPS6052056A JP15980883A JP15980883A JPS6052056A JP S6052056 A JPS6052056 A JP S6052056A JP 15980883 A JP15980883 A JP 15980883A JP 15980883 A JP15980883 A JP 15980883A JP S6052056 A JPS6052056 A JP S6052056A
- Authority
- JP
- Japan
- Prior art keywords
- cathode electrode
- chip
- thyristor
- emitter
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 230000002787 reinforcement Effects 0.000 claims abstract description 9
- 230000003014 reinforcing effect Effects 0.000 claims description 7
- 230000002093 peripheral effect Effects 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 5
- 239000013078 crystal Substances 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 230000002159 abnormal effect Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- -1 for example Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41716—Cathode or anode electrodes for thyristors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体サイリスタ、特に平形サイリスタに関す
る・
第１図は従来の平形サイリスタのサンドイッチ構造図で
あって、例えばＮ形シリコン単結晶基板の両面からアク
セプタ不純物、例えばＧａｖ熱拡散して、Ｐベース２．
Ｐエミッタ３、及びＮペース１（単結晶基板を用いる）
を形成し、次にＰベース側から、ドナー不純物、例えば
リンを選択拡散することによｐ、Ｎエミッタ４を形成し
、この時、Ｎエミッタ内に多数のＰペース露出部５を形
成し、サイリスタチップを製造する。このようにして製
造したサイリスタチップにアノード電極６、カソード電
極７．ゲート電極８を例えばアルミニウムの蒸着により
設け、熱膨張係数の等しい１対の熱補強板９．１０の間
にろう付けし、サンドイッチを構成する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor thyristor, particularly a flat thyristor. FIG. Diffusion, P base 2.
P emitter 3 and N pace 1 (using single crystal substrate)
Then, a donor impurity, for example, phosphorus, is selectively diffused from the P base side to form a P,N emitter 4, and at this time, a large number of P paste exposed portions 5 are formed in the N emitter, Manufactures thyristor chips. The thyristor chip manufactured in this manner has an anode electrode 6, a cathode electrode 7. The gate electrode 8 is provided by, for example, vapor deposition of aluminum, and is brazed between a pair of thermal reinforcement plates 9 and 10 having the same coefficient of thermal expansion to form a sandwich.
このようにして構成されたサンドイッチの表面電界強度
を下げるためにボディティブもしくはネガティブにチッ
プ周辺部をベベルカットし、さらに、ベベルカット時の
チップ周辺部の損傷を取り除くために、混酸によシチッ
プ周辺部を２０μ〜３０μエツチングしている。ところ
が、このような構造の場合、前記エツチング後において
上部熱補強板の周辺部の局部的温度上昇によ）チップの
補強板周辺部が局部的に、異常エツチングされ、第２図
に示すような形状となシ、降服電圧の低下、及び耐圧劣
下の小回となる・本発明の目的は降服電圧の低下や耐圧
の劣化のない半導体サイリスタを得ることにある。In order to reduce the surface electric field strength of the sandwich constructed in this way, the periphery of the chip is bevel cut using a body tive or negative method, and in order to remove damage to the periphery of the chip during bevel cutting, the periphery of the chip is cleaned with a mixed acid. The part is etched by 20μ to 30μ. However, in the case of such a structure, after the etching, the area around the reinforcing plate of the chip is locally abnormally etched due to a local temperature rise in the area around the upper thermal reinforcing plate, resulting in a problem as shown in FIG. Due to the shape, the breakdown voltage decreases and the withstand voltage deteriorates to a small extent.An object of the present invention is to obtain a semiconductor thyristor that does not have a decrease in the breakdown voltage or deteriorate the withstand voltage.
本発明によれば、このような不都合を取シ除くために、
チップの熱補強板周辺部にカソード電極周辺部と重複す
るように絶縁層を設け、カソード電極周辺部と絶縁層に
よりチップの上部熱補強板の周辺部を保護し、局部的異
常エツチングを防止した半導体サイリスタを得る。According to the present invention, in order to eliminate such inconvenience,
An insulating layer is provided around the thermal reinforcement plate of the chip so as to overlap with the area around the cathode electrode, and the area around the cathode electrode and the insulating layer protect the area around the upper thermal reinforcement plate of the chip to prevent local abnormal etching. Obtain a semiconductor thyristor.
次に図面を参照して本発ＢＡ＝ｆ−，１詳ＭＢに説明す
る。Next, the present invention BA=f-, 1 detailed MB will be explained with reference to the drawings.
第３図は、本発明の一実施例によるサイリスタチップを
示すもので、Ｎ形シリコン単結晶基板の両面から、アク
セプタ不純物、例えばＧａを熱拡散シて、Ｐベース】２
、Ｐエミッタ１３を形成し、単結晶基板そのものはＮペ
ース１１とし、次にＰベース側からドナー不純物である
例えばリンを選択拡散することによシ％Ｎエミッタ１４
を形成する。この時、Ｎエミッタ１４内に多数のＰペー
ス露出部１５を形成する。このようにしてサイリスタチ
ップを製造する。次に、チップ周辺部に絶縁層、例えば
Ｓ１０．膜１６を形成し、アノード電極１７、絶縁層１
６と周辺部が重複しているカソード電極１８、及びゲー
ト電極１９を例えばアルミニウムの蒸着によシ設け、熱
膨張係数の等しい１対の補強板２０．２１の間にろう付
けしてサンドインチ構造を形成する。このようにして構
成されたサンドイッチ構造の周辺部をボディティプ、ネ
ガティブにベベルカットした構造とする。FIG. 3 shows a thyristor chip according to an embodiment of the present invention, in which acceptor impurities, such as Ga, are thermally diffused from both sides of an N-type silicon single crystal substrate to form a P base]2.
, a P emitter 13 is formed, the single crystal substrate itself is an N paste 11, and then a donor impurity such as phosphorus is selectively diffused from the P base side to form a %N emitter 14.
form. At this time, a large number of P paste exposed portions 15 are formed within the N emitter 14. In this way, a thyristor chip is manufactured. Next, an insulating layer is formed around the chip, for example, S10. A film 16 is formed, an anode electrode 17, an insulating layer 1
A cathode electrode 18 and a gate electrode 19 whose periphery overlaps with 6 are provided by, for example, vapor deposition of aluminum, and brazed between a pair of reinforcing plates 20 and 21 having the same coefficient of thermal expansion to form a sandwich structure. form. The periphery of the sandwich structure constructed in this manner has a body tip and a negative bevel cut.
上記実施例から、明らかなように、本発明によればカソ
ード電極周辺部と重複する絶縁層と、カソード電極の周
辺部によシ、チップの上部補強板周辺の異常エツチング
をなくすることができ、耐圧劣化を防止することができ
る。As is clear from the above embodiments, according to the present invention, it is possible to eliminate abnormal etching in the insulating layer that overlaps with the periphery of the cathode electrode, the periphery of the cathode electrode, and the periphery of the upper reinforcing plate of the chip. , it is possible to prevent breakdown voltage deterioration.
第１図は従来の平形サイリスタのベベルカット後のサン
ドイッチ構造の断面図である・第２図は従来の平形サイ
リスタのエツチング後のサンドイッチ構造の断面図であ
る。第３図は本発明の一実施例によるサイリスタチップ
構造の断面図である・
１・・・・・・Ｎペース、２・・・・・・Ｐペース、３
・・・・・・Ｐエミッタ、４・・・・・・Ｎエミッタ、
５・・・・・・Ｐエミッタ露出部、６・・・・・・アノ
ード電極、７・・・・・・カソード電極、８・・・・・
・ゲート電極、９・・・・・・アノード側熱補強板、１
０・・・・・・カソード側熱補強板、１１・・・・・・
Ｎペース、１２・・・・・・Ｐベース、１３・・・・・
・Ｐエミッタ、１４・・・・・・Ｎエミッタ％１５・・
・・・・Ｐエミッタ露出部、１６・・・・・・絶縁層、
１７・・・・・・アノード電極、１８・・・・・・カソ
ード電極、１９・・・・・・ゲート電極、２０・・・・
・・アノード側補強板、２１・・・・・・カソード側補
強板。
５−FIG. 1 is a sectional view of a sandwich structure of a conventional flat thyristor after bevel cutting. FIG. 2 is a sectional view of a sandwich structure of a conventional flat thyristor after etching. FIG. 3 is a cross-sectional view of a thyristor chip structure according to an embodiment of the present invention. 1...N pace, 2...P pace, 3
...P emitter, 4...N emitter,
5... P emitter exposed part, 6... Anode electrode, 7... Cathode electrode, 8...
・Gate electrode, 9... Anode side thermal reinforcement plate, 1
0... Cathode side heat reinforcement plate, 11...
N pace, 12...P base, 13...
・P emitter, 14...N emitter% 15...
...P emitter exposed part, 16...Insulating layer,
17... Anode electrode, 18... Cathode electrode, 19... Gate electrode, 20...
... Anode side reinforcing plate, 21... Cathode side reinforcing plate. 5-
Claims (1)
プが第１の主面にアノード電極を又第２の主面にゲート
電極とカソード電極とを具備し、１対の熱補強板の間に
ろう付けされ、さらに１対の放熱体により、加圧接触さ
れてなるサイリスタにおいて、前記半導体チップの前記
カソード電極側の熱補強板周辺部に、前記カソード電極
周辺部と重なる絶縁膜を有することを特徴とする半導体
サイリスタ。A semiconductor chip having four consecutive adjacent layers of PNPN is provided with an anode electrode on a first main surface and a gate electrode and a cathode electrode on a second main surface, and is brazed between a pair of thermal reinforcing plates. Further, in the thyristor which is brought into pressure contact with a pair of heat radiators, the thyristor is characterized in that an insulating film is provided around the heat reinforcement plate on the cathode electrode side of the semiconductor chip, overlapping with the peripheral part of the cathode electrode. semiconductor thyristor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15980883A JPS6052056A (en) | 1983-08-31 | 1983-08-31 | Semiconductor thyristor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15980883A JPS6052056A (en) | 1983-08-31 | 1983-08-31 | Semiconductor thyristor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6052056A true JPS6052056A (en) | 1985-03-23 |
Family
ID=15701703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15980883A Pending JPS6052056A (en) | 1983-08-31 | 1983-08-31 | Semiconductor thyristor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6052056A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6347253A (en) * | 1986-08-13 | 1988-02-29 | Sumitomo Heavy Ind Ltd | Automatic paper connecting device for delivery machine |
| CN102629510A (en) * | 2011-02-04 | 2012-08-08 | 株式会社鹭宫制作所 | Molded coil and solenoid controlled valve using the same |
-
1983
- 1983-08-31 JP JP15980883A patent/JPS6052056A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6347253A (en) * | 1986-08-13 | 1988-02-29 | Sumitomo Heavy Ind Ltd | Automatic paper connecting device for delivery machine |
| CN102629510A (en) * | 2011-02-04 | 2012-08-08 | 株式会社鹭宫制作所 | Molded coil and solenoid controlled valve using the same |
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