JPS6051952A - Parity checking system - Google Patents

Abstract

PURPOSE:To execute easily the change of a parity check code accompanied with the change of a data by constituting so that a parity code is generated in advance basing on a corresponding data and stored in a random access memory in a data transmitting device. CONSTITUTION:The parity check code (p) to be added to a data (d) which is extracted from a read-only memory M1 and sent out to a data transmission line DL is generated in advance by a parity check code generating circuit PG', and stored in a random access memory M3. Accordingly, even in case the data (d) is changed, it is possible to update the parity check code (p) stored in the memory M3 by generating immediately the corresponding parity check code (p).

Description

DETAILED DESCRIPTION OF THE INVENTION (al) Technical Field of the Invention The present invention relates to a data transmission device, and in particular, to a data transmission device that easily changes a corresponding parity check code when data stored in a semi-permanent storage device is changed. Regarding the parity check method that makes it possible.

Prior Art and Problems FIG. 1 is a diagram showing an example of a conventional parity check method in this type of data transmitter. In FIG. 1, the transmitting device wlSND includes a memory M1 for continuous output that stores data d that should not be transmitted at each address a, and a parity check code p generated in advance based on a predetermined check rule corresponding to the data d. A continuous read only memory M2 is provided to store data at the same address a as the data d. When a predetermined address a is input to the continuous output dedicated memories M1 and M2,
The data d stored in the address a is extracted from the continuous output memory M1 and sent to the data transmission path DI, and the parity check code stored in the 71 address a is extracted from the continuous output memory M2. p is extracted and sent to the parity check code transmission path Pl. On the other hand, receiving device R
In the EC, the parity check code generation circuit PG generates a parity check code !+p from the data (1') arriving from the data transmission path DI7 based on the above-mentioned check rule, and transmits it to the exclusive OR gate EG. Wa Gate EG is
Exclusive OR processing is performed on the parity check code p arriving from the parity check code transmission path PL and the parity check code p' transmitted from the parity check code generation circuit 28-pc, and both parity check codes p and p are processed. If the logical values of the parity check codes p and p'' match, the parity check output signal Ck is set to a logical value of 0, indicating that there is no error in the arrived data d', and if the logical values of both parity check codes p and p'' match, If not, the parity check output signal ck is set to a logical value of 1 to indicate that an error has occurred in the arrived data d1.

As is clear from the above explanation, in a conventional parity check method, the parity check code p corresponding to the data d stored in the read-only memory M1 is stored in advance in the read-only memory M2, and the data d is extracted. When the parity check code p is extracted, the corresponding parity check code p is extracted. Therefore, if the data d in the read-only memory M1 is changed for some reason, the corresponding parity check code p in the read-only memory M2 must also be changed at the same time.

However, the read-only memory M2 has the drawback that the stored contents cannot be easily changed.

(C1 Purpose of the Invention The present invention is a parity check method that eliminates the drawbacks of the conventional parity check methods as described in It is about realizing.

++11 Structure of the Invention This object is to extract data previously stored in a semi-fixed memory 1a device, add a parity check code, and transmit the data, in which a parity check code corresponding to the data is generated in advance. By storing the parity check code in the continuous write memory at any time, and when extracting the data from the semi-permanent storage device, extracting the corresponding parity check code from the continuous write memory and adding it to the data and transmitting it. achieved.

(el　Embodiments of the invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram illustrating a parity check method according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures. In FIG. 2, the transmitting device SND includes a parity check code generation circuit PG' and an occasional write/read memory M3.
, and the read-only memory M2 as shown in FIG. 1 has been removed. In FIG. 2, before entering the transmitting state, the transmitter SND sequentially extracts data d stored in each address a of the read-only memory M1 and transmits it to the parity check code generation circuit PC''. The generation circuit PG'' generates the transmitted data d
A parity check code p corresponding to is generated based on a predetermined check rule, and transmitted to the read/write memory M3 as needed. The transmitting device SND inputs the same address a and the write signal W inputted into the read-only memory M1 into the write/read memory M3 at any time, so that the transmitted parity check code p is stored at the same address a as the corresponding data d. Store in. When the parity check code p corresponding to all the data d stored in the read-only memory M1 is written as needed and stored in the read-out memory M3, the transmitting device SND enters the transmitting state. When a predetermined pulse a is input to the read-only memory M1 and the occasional write/read memory M3 in the overloaded state, the data d extracted from the read-only memory M1 is sent to the data transmission path DI, and The parity check code p read from the read/write memory M3 at any time is sent to the parity check code transmission path PL. Receiving device RF
In C, the parity check code generation circuit PG generates a parity check code p1 from data (1) arriving from the data transmission path DI, as in FIG. code transmission path p t,
Exclusive OR processing is performed on the parity check code p arriving from the parity check code p'' generated by the parity check code generation circuit PG to check the normality of the data d', and the logic value of the parity check output signal ck is determined. Set.Sending device SN
In D, when the data d in the read-only memory Ml is changed, the transmitting device SND again generates a parity check code p corresponding to the changed data d by the parity check code generation circuit PC', and writes it as needed. The data is stored in the continuous output memory M3.

As is clear from the above description, according to this embodiment, the parity check code p added to the data d extracted from the read-only memory M1 and sent to the data transmission path DL is generated by the parity check code generation circuit PG°. Since it is generated in advance and stored in the read/write memory M3 at any time, even if data d is changed, the corresponding parity check code p is immediately regenerated by the parity check code generation circuit PG', and the code is stored in the memory M3 for write/read at any time. The parity check code p stored in M3 can be updated.

Note that FIG. 2 is only one embodiment of the present invention, and for example, the configurations of the transmitting device SND and the receiving device REC are not limited to those shown, and many other modifications may be considered. However, in either case, the effects of the present invention remain the same.

(fl) As described above, according to the present invention, in the data transmitting device,
Since the parity check code is generated in advance based on the corresponding data and stored in the read/write memory as needed, it can be easily changed as the data changes.

[Brief explanation of drawings]

Section 0.1 A diagram showing an example of a conventional parity check method,
FIG. 2 is a diagram showing a parity check method according to an embodiment of the present invention. In the figure, 2I is an address, ck is a parity check output signal, j-1d and dl are data, DL is a data transmission line, EG is an IJI logic sum game I, M1 and M2 are read-only memories, and M3 is an optional memory. write/read memory, p
and p' is a parity check code, PG and PC" are parity check code generation circuits, PI is a parity check code transmission path, REC is a receiving device, and 5Nr) is a transmitting device.

Claims (1)

[Claims] In a data transmitting device that extracts data stored in a semi-permanent storage device in advance, adds a parity check code, and transmits the data, a parity check code corresponding to the data is generated in advance and stored in a read/write memory as needed; extracting a corresponding parity check code from the continuous write memory when extracting the data from the semi-permanent storage;
A parity check method characterized in that the parity check method is added to the data and sent.