JPS6051372A - Clamping circuit - Google Patents

Abstract

PURPOSE:To prevent generation of a sag, etc. by constituting a titled circuit so that an DC bias of an input side of an active element for amplifying a signal which has been clamped is not applied except a clamp period. CONSTITUTION:A switching transistor Q4 and a clamping transistor Q3 are interlocked with a pulse period of a clamping pulse and execute an on-operation, and a clamp voltage of a set point is supplied to a signal path 1 through an emitter-collector path of the clamping transistor Q3. When this clamp voltage is charged to a coupling capacitor C1, a DC voltage is superposed onto a waveform part synchronizing with a clamp pulse of a video signal, and a clamping operation is executed. When the clamp pulse is not supplied, the weitching transistor Q4 and the clamping transistor Q3 maintain an off-state, and a DC bias from a bias resistance R4 of an output transistor Q2 is not impressed either, therefore, a clamp voltage charged to a coupling capacitor C1 becomes a base voltage of the output transistor Q2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a clamp circuit, and for example, to a clamp circuit in a television receiver that aligns synchronization signal levels of video signals.

[Technical background of the invention]

In general, in communication equipment such as television receivers, some of the signals to be transmitted are fixed at a constant voltage, the DC component is varied between the input stage and the output stage, and the DC component lost at the input stage is transferred to the output stage. There are times when you want to play the disc and take it out. Fixing and changing the DC component like this.

The reproduction circuit is one of the important circuits that affects color reproducibility, especially in color television receivers.

As shown in Fig. 1, the conventional clamp circuit has input terminal 1.
The video signal applied to is led out to the input path of the output transistor (h) through the pre-transistor Ql. A coupling capacitor C is inserted in this input path, and the coupling capacitor C! and the base of the output transistor Qz The collector of the clamping transistor Q3 is connected to the signal path 2 connecting the two.

This clamping transistor Q3 has a capacitor am connected between its emitter and a ground point, and a resistor R inserted between the emitter and the power supply terminal 3 and the ground point.
, R, are connected. Further, the clamp transistor Q3 is connected to a control terminal 4 via a resistor R3, and is switched by a clamp pulse applied to the control terminal 4.

Furthermore, a resistor R is connected between the power supply terminal 3 and the signal path 2.
4 is connected, and this resistor R4 serves as a bias resistor that determines the operating point of the output transistor Q2.

In addition, the collectors of each of the front and output transistors Q*-(hu are connected to the power supply terminal 3, and each resistor RsrR6 is provided between each emitter and the ground point.
The output of the front transistor Qs is taken out from the emitter.

The clamp circuit configured as described above operates by clamping the pulse applied to the control terminal 4, for example, during the pulse period of a horizontal synchronizing pulse formed by synchronously separating a video signal or a flyback pulse from a flyback transformer (not shown). The collector-emitter circuit of the transistor Q3 is closed, and the divided voltage of the resistors R1e and R4 set at its emitter is supplied to the signal path 2 as a clamp voltage, and this clamp voltage is applied to the coupling capacitor C! By charging the transistor Q2, a signal in which, for example, the top or pedestal level of the synchronizing signal of the video signal is adjusted to a constant DC level is outputted from the output transistor Q2. However, the coupling capacitor C1 is connected to the output transistor Q! so that the charged clamp voltage is not discharged at least during the vertical scanning period of the video signal. Input impedance etc. are set.

[Problems with background technology]

The above conventional circuit is based on the assumption that a clamp pulse is supplied, and if the clamp pulse is no longer supplied for some reason, the clamp transistor Qs will continue to be turned off, and the base voltage of the output tube transistor Q2 will be Resistance R
4, it increases to a value determined by the following formula.

In the above equation, VBE is the base-emitter voltage of the output transistor Qz, and R4*R6 are the resistors R4e and R6, respectively.
4 resistance value, hfe is the DC amplification factor of the output transistor,
VCC is a power supply voltage applied to the power supply terminal 3.

When the base voltage of the output transistor Q increases to such a value, and the video signal derived from the output transistor Q2 is of positive polarity, the collector current increases, resulting in an increase in the beam current of the cathode ray tube, and the screen suddenly became brighter,
If a brightness limiting circuit is not provided, the high voltage circuit will be overloaded.

To improve this point, there is a clamp circuit with a different bias method for the output transistor (h) as shown in Figure 2. Figure 2 shows the output transistor (Q) of the circuit in Figure 1.
A resistor R7 is provided between the base of 2 and the ground point,
Other identical members are indicated by the same symbols.

In this way, even if the clamping transistor Q3 continues to be turned off without being supplied with a clamp pulse, the base voltage of the output transistor Q2 is maintained at a certain voltage, and an increase in the collector current can be prevented.

However, in the circuit of FIG. 2, the coupling capacitor C1
Since the resistor R7 is provided in the path that affects the discharge time constant of
The value of resistor R7 must be relatively large,
The base voltage in equation (2) can only be determined to be approximately the same voltage as the value at which the base voltage of output transistor Q2 increases (see equation (1)) in Fig. 1. If this is done, the discharge time constant becomes smaller than the vertical scanning period of the video signal, resulting in a waveform waveform and screen shake.

In addition, the emitter voltage of the clamping transistor is added to the base voltage determined by equation (2), that is, resistor R1v R4% capacitor C! If the clamp level voltages set in are made close to each other, the reproduced DC voltage will not fluctuate and the clamp waveform will not have any dips, but there is a problem that a large dynamic range cannot be obtained.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned points, and even if the clamp pulse is not supplied for a long period of time, the DC level fluctuations such as dips will not occur in the clamped signal, and it can be used sufficiently as a clamp waveform. The purpose of the present invention is to provide a clamp circuit that can be used as a clamp circuit.

[Summary of the invention]

That is, in the present invention, in a clamp circuit that aligns the main signal to the clamp voltage via the coupling capacitor to the input path of the active element, a clamp pulse for charging the coupling capacitor with the clamp voltage is supplied for a long period of time. The input side bias voltage of the active element is set to zero potential when the active element is no longer active. As a configuration for this purpose, for example, a collector-emitter path of the first transistor and a resistor in series with this path are connected between the input path after the coupling capacitor of the active element and the reference potential point, and a set point of the clamp voltage is connected. For example, a collector-emitter path of a second transistor is connected between each first . A clamp pulse is applied to the base of each second transistor to control the voltage of the waveform portion to be clamped to the clamp voltage level, and when the clamp pulse is no longer input, the discharge voltage of the clamp voltage charged in the coupling capacitor is applied. An input side bias voltage of the active element is applied, and after the clamp voltage is discharged, the input side bias voltage of the active element becomes zero potential.

[Embodiments of the invention]

Hereinafter, the present invention will be described with reference to illustrated embodiments.

FIG. 3 is a circuit diagram showing a clamp circuit according to a basic embodiment of the present invention. Note that the same reference numerals are used for the same elements as in FIG. A video signal is supplied to the input terminal 1. This input terminal l is connected to the base of the front transistor Q1. The collector of this front transistor Qs is connected to the power supply terminal 3, and the emitter is grounded via a resistor Rs. The video signal is derived from the emitter and supplied to the base of the output transistor Q via the coupling capacitor C1. This output transistor Q! The collector is connected to the power supply terminal 3, and the emitter is grounded via a resistor R6.

A switching transistor Q4 having a bias resistor R4 connected in series with the collector-emitter path is provided between the signal path 2 from the coupling capacitor CI to the base of the output transistor f'Qt and the power supply terminal 3, A resistor Rs is connected to the base of this switching transistor Q4.
A horizontally periodic clamp pulse is applied from the control terminal 4 through the control terminal 4.

9- Furthermore, a series circuit of resistors R2+R1 is connected between the power supply terminal 3 and the ground point, and a capacitor C2 is provided in parallel on the resistor R2 side. These resistances R,,R.

A connection point between capacitor CtFi and resistors R1 and R2 is set as a set point, and a clamp voltage is formed at this set point. A clamping transistor Q3 with a collector-emitter path inserted is provided between this set point and the signal path 2, and this clamping transistor Q3
The clamp pulse is applied to the base of the resistor R3 through the resistor R3.

According to the clamp circuit configured as described above, the switching transistor Q4 and the clamping transistor Qsu turn on in conjunction with the pulse period of the clamp pulse, and M1
The configuration is the same as that of the circuit shown, that is, the bias resistor R4 is now connected between the power supply terminal 3 and the signal path 2, and the set point is now connected to the signal path 2 through the emitter-collector path of the clamping transistor Q3. clamp voltage is supplied. This clamp voltage is the coupling capacitor C1
By being charged to , the clamp pulse 1 of the video signal
A DC voltage is superimposed on the waveform portion synchronized with 0-, and a clamping operation can be performed. A video signal obtained by reproducing this DC voltage is derived from the collector of the output transistor Q2, for example.

Now, if the clamp pulse is no longer supplied for some reason, the switching transistor Q4 and the clamping transistor Q3 will remain off.
Since no direct current bias is applied from 5 to 5, the clamp voltage charged in the coupling capacitor CI becomes the base voltage of the output transistor Q2. This clamp voltage is gradually discharged and superimposed on the video signal to perform a clamp operation. The discharge time constant at this time is C11hfe-R6, where C is the capacitance of the coupling capacitor CI.
・・・・・・－・・・・・・・・・・・・・・・・・・
As determined by (3), since the vertical scanning period is sufficiently long, it is unlikely that it will significantly affect the video signal. Further, if the clamp pulse is not supplied even after the elapse of time based on this time constant, the base voltage of the output transistor Q2 becomes zero.

As a result, the output transistor Q2 is cut off,
Since the collector current no longer flows, the cathode ray tube cathode voltage increases and the beam current of the cathode ray tube can be cut off. In this way, the present invention can obtain a clamp waveform with no DC level fluctuation even if the clamp pulse is no longer used.

Note that the clamp pulse is obtained by, for example, synchronizing the horizontal synchronization pulse included in the synchronization signal period in a video signal with the waveform part to be clamped (synchronization tip, pedestal level part, etc.) by delaying or other means. be.

Next, specific examples will be described. FIG. 4 is a circuit diagram of a clamp circuit showing a specific embodiment of the present invention. Note that the same elements as in FIG. 3 are denoted by the same reference numerals. The output stage of this circuit commonly connects the emitter of transistor Q5 and the collector of transistor Q2, the emitter of transistor Q is provided with a parallel circuit of resistor R6 and capacitor C3, and the base of transistor Q5 is connected to power supply terminal 5. The transistor Q5 is connected to the connection point of the series circuit of the resistor RIO and the voltage regulator diode D1 connected between the ground point and the zener voltage from the voltage regulator diode D1 at this connection point.
A base bias is applied to the transistor Q5, and the power supply voltage of the power supply terminal 5 is applied to the collector of the transistor Q5 via the resistor R11 to drive the two output transistors Qs and Qz.
A clamp waveform is output from the collector of the transistor Q5 through the multi-output terminal 6. Here, the capacitor cm is a capacitor for improving the frequency characteristics of the circuit.

Further, a coupling capacitor Cs is connected to the path connecting the emitter of the front transistor Ql and the base of the transistor Q2.
and a resistor R9 are connected in series, and the emitter of the switching transistor Q4 and the collector of the clamping transistor Qs are connected to the connection point between the coupling capacitor C1 and the resistor R9. Switching transistor Q4
The collector has a bias resistor R4 between the power supply terminal 3, and a clamp pulse is applied to its base via a resistor R8, while a clamp transistor Q3
A series connection of a resistor R1 and a diode D-13- is inserted between the emitter of the power supply terminal 3, and a resistor R2 and a capacitor are connected between this emitter and the set point of the clamp voltage. A parallel circuit of C2 is connected. Furthermore, a clamp pulse is applied to the base of the clamping transistor Q3 via a resistor R3, and a resistor R11 is provided between the base and the ground point.

In the above configuration, a resistor R9 is provided between the coupling capacitor C8 and the base of the transistor Q2 to prevent oscillation of the circuit, and a resistor R1 connected to the base of the clamp transistor Q3 is provided to reduce the storage time of the transistor. However, the diode D2 is for compensating for variations in clamp voltage with respect to temperature. In this circuit, the accumulation time during turn-off of the clamp transistor Q3, which is turned on by the clamp pulse, is reduced.
The clamp voltage is superimposed only on the waveform part that should be clamped,
Moreover, this clamp voltage does not vary depending on temperature. And even if the clamp pulse is no longer supplied,
As long as the coupling capacitor C1 is charged with a clamp voltage of 14-, the clamping operation is performed, and when the base 'M, l:r' of the transistor Q2 becomes zero, the transistor Q2 is cut off, and then the transistor Q is also cut off. Therefore, a clamped waveform with no DC level fluctuation can be derived to the output terminal.

In addition, the waveform portion to be clamped refers to the synchronization tip or the pedestal level portion on both sides of the pedestal in the case of a positive video signal.For example, the entire position of the horizontal synchronization pulse or flyback pulse is clamped to this portion. be.

〔Effect of the invention〕

As explained above, according to the present invention, since the DC bias on the input side of the active element that amplifies the borrowed scenery after clamping is not applied except during the clamping period, when the clamping pulse is no longer supplied to the clamping circuit, A clamping operation is performed by a clamping voltage caused by discharging a coupling capacitor, and when this clamping voltage is discharged and becomes double, the active element is cut off and a good ramp waveform can be formed without causing sag.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a conventional clamp circuit, Fig. 2 is a circuit diagram showing another conventional example, Fig. 3 is a circuit diagram showing a clamp circuit according to a basic embodiment of the present invention, and Fig. 4 is a circuit diagram showing the present invention. FIG. 2 is a circuit diagram showing a clamp circuit according to a specific embodiment of the invention. Ql-Qs-...Transistor, R1-R12...Resistor, CI, C2...Capacitor, D1+D2...Diode. Representative Patent Attorney Kensuke Norichika (and 1 other person) ^+ (('1 - W

Claims (2)

[Claims] (1) A coupling capacitor is inserted in the input path of the active element, and the signal passing through this coupling capacitor is clamped with a clamp pulse synchronized with the waveform portion so that the clamp voltage is superimposed on the waveform portion to be clamped. a clamp circuit that clamps the signal by charging the clamp voltage to the coupling capacitor during the pulse period of the clamp pulse, and clamping the signal to the path connecting the active element and the coupling capacitor; 1. A clamp circuit comprising bias means for applying a discharge voltage of a clamp voltage charged to said coupling capacitor as an input bias voltage of said coupling capacitor. (2) The bias means connects a switching circuit of a first three-terminal switching element having a control electrode between a path connecting the active element and the coupling capacitor and a reference potential point, and a resistor connected in series to the switching circuit. , and a switching circuit of a second three-terminal switching element is connected between the set point where the clamp voltage is set and the special path, and the switching circuit of the second three-terminal switching element is connected to the control electrode of the winter first and second three-terminal switching elements, respectively. The clamp circuit according to claim 1, wherein the clamp circuit is configured to apply the clamp pulse.