JPS6050969A - Field effect transistor - Google Patents

Abstract

PURPOSE:To obtain an FET which has less parasitic capacity between a source and a gate by providing a laminated region of a region having high impurity density and a region having the same conductive type disposed under the previous portion but slightly lower impurity density, and covering the region with source and drain regions. CONSTITUTION:An N type Al0.3Ga0.7As layer 2 to become a channel is formed on a central surface layer of a high resistance GaAs substrate 1, and a channel layer 3 of the secondary electron layer modulation-doped by the difference of electric anionic degree to between the layer 2 and GaAs is formed under the layer 2 simultaneously. Then, N type Al0.3Ga0.7As regions 5 of 1X10<18>/cm<3> of impurity density are laid at both sides of the layer 2, thereby forming N type GaAs region 4 of 2X10<18>/cm<3> of density is formed. Subsequently, a gate electrode 6 is formed on the layer 2, and source electrode 7 and drain electrode 8 are covered on the region 4. Thus, the voltage applied to the electrode 6 is controlled to set the electric conductivity of the layer 3 to the prescribed value.

Description

[Detailed description of the invention] The present invention relates to field effect transistors.

In order to achieve ultra-high speed field effect transistors (FETs), it is important to shorten the gate length and reduce the parasitic resistance between the source and gate.

An object of the present invention is to provide an FET with low parasitic resistance between source and gate and low substrate current.

In the present invention, the first high impurity concentration region made of the first semiconductor is provided adjacent to the channel in the length direction, and is in contact with the lower part of the high impurity concentration region of Hl, and is made of the first semiconductor. A high impurity concentration region made of a second semiconductor having low electronegativity is provided 9, and an electrode metal layer serving as a current supply source is formed on the surface of the first high impurity concentration region.

In the structure of the present invention, carriers in the second high impurity concentration region move into the first high impurity concentration region adjacent to the channel direction due to the difference in electronegativity. The carrier concentration increases more than the amount of impurity doped. As a result, if the thickness of the second high impurity concentration layer, which has the feature of reducing the parasitic resistance between the source and gate, is appropriately selected, sufficient carriers can be induced in the first high impurity concentration layer, and Most of the carriers in the high impurity concentration layer of No. 2 can be depleted. As a result, in the structure of the present invention, the current flowing through the substrate under the channel layer can be reduced even though the high concentration layer is formed in a region deeper than the region where the channel layer is formed. Therefore, the electrode structure of the present invention has the advantage of reducing the substrate current as well as reducing the parasitic resistance.

The present invention will be described in detail below using the drawings.

FIG. 1 shows a cross-sectional structure of a modulation doped FET having the structure of the present invention. A high-resistance GaAs layer 2 is formed on the substrate 1 with a Kn-type impurity concentration I x 10''cm-' r thickness of 500 people, 3GaO,?As layer 2, n/!'
0.30 ao, 7 A High resistance Ga A due to the modulation Dogg effect due to the difference in electronegativity between S and GaAs
s U of substrate 1. A two-dimensional electronic layer is formed at the interface where 1g ()aO,7As layer 2IC contacts. The channel layer 3 shown in FIG. 1 is formed by these two-dimensional electrons. The electrical conductivity of the channel layer 3 is AA, s Ga
o,yA can be controlled by the 'voltage applied to the d' electrode 6 provided on As, and thus operates as a FET. In the embodiment of FIG. 1, the channel layer 3 and AZo,
s GaO, T A n-type impurity concentration 2 in contact with s layer 2
A GaAs region 4 with a thickness of 100 OA is installed, and in contact with this Ga As region 4, Aj!o, B with an n-type impurity concentration of 1×10' G aQ, 7 A @ region 5 is installed. Due to the modulation doping effect, M., 3G36.7 people S
The region 5 is depleted, and electrons are induced in the GaAs region 4 in contact with it.

Therefore, the high impurity concentration GaAs in contact with the channel layer 3
The electron concentration in region 4 is higher than the doped impurity concentration. An Au-Ge alloy film is formed on the surface of the GaAs region 4, and serves as a source electrode 7, respectively. The drain electrode 8 is shaped by photolithography. In the embodiment shown in FIG. 1, the electron concentration of the high impurity concentration GaAs region 4 in contact with the channel layer 3 is 0.05. , 3GaO, 7As region 5, the parasitic resistance between the source and gate electrodes and between the drain and gate electrodes is reduced. Therefore, the modulation doped FET of this embodiment operates at high speed. Furthermore, in this example, the high impurity concentration G a As
Since the Alo, 5Gao, and yAs regions 5 below the region 4 are depleted, the electrons injected into the source electrode 7 also reach the substrate 1.
It does not flow into the drain current [8] through the drain current. Therefore, the FET (7) exhibits excellent saturation characteristics and high-speed operation. AI-o,s Gao,? In order to form the As layer 5 and the GaAs region 4, it is advantageous to use a selective growth technique such as molecular beam epitaxy or organometallic chemical vapor deposition, which has excellent film thickness controllability.

FIG. 2 shows a cross-sectional structure of a Schottky gate field effect transistor (MESFET) which is a second embodiment of the present invention, and shows a high resistance GaAs substrate 1 with Kn-type impurity concentration 2xlO"crn-' + thickness A 200OA GaAs layer is formed, and an M gate electrode 6 is placed on its surface.The Schottky barrier property between M and GaAs allows the G
aA s is divided into a depletion layer 9 and a channel layer 31. This division ratio changes depending on the voltage applied to the gate electrode 6, and the electrical conductivity of the channel layer 31 is controlled.
Operates as a FET. In the embodiment shown in FIG. 2, an n-type impurity concentration of 2×10” Cr
A GaAs region 4 with a thickness of 2000A is provided, and is in contact with the GaAs region 4, with an n-type impurity concentration lx.
loI8cm-" *Thickness 300A 'o, 5Gao,
A yAs area 5 is installed. Due to the modulation doping effect, the O, 5 Gao, yAs region 5 is depleted, and electrons are induced in the GaAs region 4 in contact with it.

Therefore, the high impurity concentration (L+A
The electron concentration in the s-region 4 is higher than the impurity concentration. AIl Ge alloy film is GaA-s BN region 4
A source electrode 7. is formed on the surface, respectively. The drain electrode 8 is shaped by photolithography. In the embodiment shown in FIG. 2, the high impurity concentration QaAs in contact with the channel layer 31 is
Calculate the electron concentration in region 4. , 3Ga(,,.

The parasitic resistance between the source and gate electrodes and between the drain and gate electrodes is reduced because of the effect of the As region 5. Therefore, the MESFET of this example
operates at high speed, and in this example, the impurity concentration is 0.
Since the A, 3Gy, 7As region 5 below the aAs region 4 is depleted, electrons injected from the source ring/soil 7 do not flow into the drain electrode 8 through the substrate 1. Therefore, the FET exhibits the characteristics of excellent saturation characteristics and high-speed operation.

The above embodiments of the present invention are modulation doped FETs.

Although MESFET has been described, it goes without saying that the present invention can also be applied to other FETs such as a junction type FET, an insulated gate type FET, and the like. In addition, as semiconductor materials, InGaAs mixed crystal, In~■s mixed crystal, or InGaAs mixed crystal,
Various F made from combinations of As mixed crystal and InP, etc.
It is also applicable to ET.

[Brief explanation of the drawing]

FIG. 1 shows a modulation doped FET which is a first embodiment of the present invention.
FIG. 2 is a diagram showing the cross-sectional structure of ME, which is the second embodiment.
Figure 7 shows the cross-sectional structure of SFET. In the figure, 1 indicates high resistance G; I
A s substrate, 2 is n-type υ. ,3Ga6.7AS'l,
3 is a channel layer formed at the interface of a high-resistance GaAs substrate, 31 is a channel layer formed in an n-type GaAs layer, 4 is a GaAs region with a high impurity concentration, and 5 is an Al2n layer with a high impurity concentration. , 3 Gan, 7AsFG, 6 gate AJ! 7 is a source Au-Ge electrode, 8 is a drain Au-Ge electrode, and 9 is a depletion layer formed in the GaAs layer. Dai J! I! A, 4r Physician Shino Hara 1 Figure

Claims (1)

[Claims] A first high impurity concentration region made of a semiconductor of @i is provided adjacent to the channel of the field effect transistor in the length direction thereof, and is in contact with the lower part of the first high impurity concentration region and is closer to the first semiconductor than the first high impurity concentration region. A field effect transistor characterized in that a second high impurity concentration region made of a second semiconductor having low electronegativity is provided, and a metal layer is provided on the surface of the first high impurity concentration region.