JPS6050796A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent malfuction even if there is a slight shift in signal timing by providing plural bit lines crossing the 1st word lines which are set divided into plural lines, and providing a selector consisting of NOR gates for selecting memory cell groups of connected plural sections. CONSTITUTION:When address signals Ak-Al are set and a row decoder 13i and a selection decoder 17' are selected, the 2nd word line WLi goes down to a level ''L'' and the output SD of a selected section selecting circuit 17 is held at the level ''L''; and the memory cell group connected to the 1st word line WLi' is activated and data is read out of or written in memroy cells through bit lines selected by the column decoder. At this time, even if the rising of the potential of the 2nd word line SWLi is delayed, the potential of the 1st word line WLi' rises corresponding to the potential variation of the 2nd word line SWLi, so the 1st word line WLi' is made inactive securely.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a high-capacity semiconductor memory device, and is particularly used for a semiconductor memory device with a large operating margin and high reliability. TECHNICAL BACKGROUND OF THE INVENTION Conventionally, as this type of semiconductor memory device, one in which memory cells are divided into a plurality of blocks as shown in FIG. 1 has been used. Note that here, a case will be described in which the memory cell group is divided into two blocks, focusing on one row (one row). In the figure, WLi and WLi' are first word lines divided into a plurality (two), and pit lines BLB+BL, ~BLn+BLn and BI, intersect with the first word lines WLi and WLi'.
', BL1'5BLn'+BLn' are provided, and the first word lines WLi, WLi'11, . 11.・
... will be installed. The above word line WLI + WLI'
A selector 12゜1! consisting of 1v(O8FETQ, , O2 and Q1'+Q2' is arranged at one end of each. The MO3FETQ, , Q1' is connected to the signal line s,
, s,' and the first words #WLi, WLi', respectively, and these IJO3FETs Qt.

The gates of Q and ' are respectively connected to the second word line 5WLi. The second word line 5WLi is supplied with an address signal Ak-Al and the output of a row decoder (NAND gate) IJi that selects a memory cell group in the row direction. Furthermore, the MO3FETs Q, Q2' are inserted between one end of the first word lines WLi, WLi' and the ground point (Vss), and their gates are connected to the signal lines S2, S2', respectively. Above signal line SI
, SI' and S2 y S2' are section decoders (NAND gates) 1 to which 1 to 80 are supplied to address signals for selecting sections of the memory cell group.
4. A NOR gate 15 to which the output signal SD of the section decoder 14 and the inhibit signal φI are supplied;
and a section selection circuit zy consisting of an inverter 16
, rf. Note that since the section selection circuits 17 and 17' have the same configuration, only one configuration is specifically shown here.

Next, the operation of the above configuration will be explained with reference to the timing chart of FIG.

Address A k-A 1 ka time to supplied to row decoder I31 and section decoder 3-14
In response to this change in address, the inhibit signal φr is maintained for a predetermined time (tl
to 12) becomes a high (%H") level. At this time,
The output i of the section decoder I4 is at a low (1L") level only in the selected section (here, it is assumed that the memory cell blocks on the side of the section decoder 1f, r2', . . . are selected). Therefore, the output SD-#x of the NOR gate 15 changes from time t1 when the inhibit signal φ is at the 1H level to t2.
-1, it is at the 'L' level. Therefore, the output 5D-fx of the inverter Z6 is at the 1H level. Assuming that the row decoder 131 is selected by the address signal Ak-Al, the potential of the second word lswLt is at the time t.
, during the period t2, the MOS
FET Q1' is turned on. Further, at time t2, the output SD-<IsI of the NOR gate 15 goes to the H level, the output SD-+)5I of the inverter 16 goes to the 1L level, and the MOS FETs Q and Q are turned off. The first word line wLt' goes to the 'H' level due to the 'H' level potential output from the NOR gate, and the memory cells 11, 11, . . . connected to the first word line WLi'.
・is activated and selected by a column decoder (not shown) i BL1' * BL1' to BLn
Data is read from or written to a predetermined bit line in ', BLn'.

Next, it is assumed that one section (a section is one block of a group of memory cells) continues to be selected by the section decoder 14, and the first word line WLi' of the selected section changes from the selected state to the unselected state. think about it. k −A to the address signal at time t3
When I changes and the inhibit signal becomes 'H' level during the period from time t4 to tll, the cutting signal S of the inverter 16 changes.
The D-convex becomes 'H' level and MOS FgTQ2' turns on.At this time, the output of the row decoder 131 is at 'H# level (non-selected state), so 1viO8FE
TQ,' is in the off state, and the first word line WLi' is at the 1L" level. Therefore, the memory cell group connected to this word line WL,' is inactivated. Next, the inhibit period) (14~ts) is completed and the inhibit signal φ returns to the 1L" level, the output SD-<IsI of the inverter 16 becomes the 1L" level, and the MOS FE
Since 'l'Q2' is in the off state, word line WLi'
'LH level is maintained, and the transition from selection to non-selection is completed.

As described above, by providing a plurality of first word lines and a second word line for selecting them, and dividing one row into a plurality of sections for selection, memories that are activated simultaneously can be This leads to a significant reduction in the number of cells and allows for a significant reduction in operating current.

[Problems with background technology]

However, in the above configuration, due to process variations, etc., the timing at which the second word line 5WLi switches from the 'L' level to the 1H level is determined by the inhibit signal φ■, as shown by the broken line in FIG. After the end of (fall to 1L" level), the output sr+-#x of the inverter 16 becomes 'L" level, and )408F
Even after ET Q2' turns off, uos FgT
The on state of Q,' is maintained. At this time, the output signal SD-$x of the NOR gate 15 is at the ``■'' level, so
Word line WL i' is charged via uos FET q2'. For this reason, since it is originally non-selected, 1
Although it should be at the L" level, the memory cell group connected to the word line wL1' remains activated when it reaches the 5" level. This not only increases wasteful power consumption, but also creates the possibility that erroneous information may be read from any of the bit lines BL, `˜BLn', since unselected memory cells are selected. That is, the operation mode at this time becomes a malfunction mode.

[Purpose of the invention]

This invention was made in view of the above circumstances,
The purpose is to provide a semiconductor memory device with a wide operating margin and high reliability, which does not cause malfunction even if there is a slight deviation in signal timing.

[Summary of the invention]

That is, in the present invention, a plurality of bit lines are provided so as to intersect with a first word line which is divided into a plurality of parts,
A memory cell group divided into a plurality of sections is provided corresponding to each intersection of the first word line and the bit line. Further, at one end of each of the plurality of first word lines, a selector consisting of a NOR gate for selecting a group of memory cells in a plurality of sections connected to the first word line is provided, and one input terminal of the selector is provided with a selector including a NOR gate. Two word lines are connected and the second word line is connected to the output end of the row decoder. Furthermore, outputs 41& of section decoders that supply section selection signals of the memory cell group are connected to the other input terminals of the selectors.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 3, the same components as those in FIG. 1 are given the same reference numerals, and their explanations will be omitted. That is, as the selector in FIG. 1, the NOR gate 18.18
'f is provided, and the section selection circuit 77 in this case
As 17', only the HAND gate (section decoder) 14 is sufficient. One input terminal of the NOR gates 18° 18' is connected to the second word line 5WLi, and the other input terminal is connected to the section selection circuit 17.
, J7'.

Next, the operation in the above configuration will be explained. Time t. When address signal Ak~ is set to 1 and the row decoder 131 and section decoder 17' are selected, the second word line WLi becomes 'L' level.
The output SD of the selected section selection circuit 77' (NAND gate 14) is maintained at the 1L level. Therefore, the output of the NOR gate Z8' becomes the H level, and the potential of the first word line WLi' becomes '1L' level. The memory cell group connected to the first word line WLi' becomes H" level and is activated. Then, the pit lines BL, '#π1' to BL
Data is read from or written to the memory cell via a pit line selected by a column decoder (not shown) among n'+BLn'. next,
When the address 8k-A1 changes (t2), the output of the row decoder 131 becomes the 5H" level, and the first word line WLi' becomes the %L" level. At this time, even if the rise of the potential of the second word line 8WLi is delayed as shown by the broken line in FIG. Since the first word line WLi falls in response to
' can be reliably inactivated.

FIG. 5 shows the NOR gate 1 B in FIG. 3,
An example of a circuit configuration when formed in a static memory having an MO8 configuration is shown.

The first and 21st JOEi of the first conductivity type (P channel type) are connected between the first potential supply source VDD and the second potential supply source VSS.
FgT Q3, Q! and a third MOS FET Q5 of the second conductivity type (N-channel type) are connected in series, and the gate of the MO8FEiT Q4*Qa is connected to the signal line SI (or S,'),
The connection point of S FET Q4 e Qi is the first word line W
LI (or wLj,'). According to such a configuration, a NOR gate can be configured with a small number of elements.

In the above-described embodiment 11, a static type semiconductor memory device has been described, but it is of course applicable to a dynamic type semiconductor memory device.

However, in the dynamic type, it is necessary to refresh each block.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to obtain a semiconductor memory device which has a wide operating margin and high reliability and does not cause malfunction even if there is a slight deviation in signal timing.

11-

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram for explaining a conventional semiconductor memory device, FIG. 2 is a timing chart for explaining the operation of the circuit shown in FIG. 1, and FIG. 3 is a semiconductor device according to an embodiment of the present invention. FIG. 4 is a circuit diagram for explaining the storage device, and FIG. 4 is a timing chart for explaining the operation of the same embodiment.
This figure is a circuit diagram showing an example of the structure of the NOR gate in FIG. 3 above. WLi, WLi'...first word line, BL, lB
L, ~BLn r BLn, BLj' r BL,
'~BLn'+ BLn - pit line, 11, 11.
...,...Memory cell, Z8゜18'...Selector (NOR gate), 5WLi...Second word line, A
kNAl, A1-Aj...address signal, 131...
- Row decoder, Z7, 17'... section selection circuit (section decoder), VDD... first potential supply source, VS19... second potential supply source, Q3 to Q6.
...1st to 4th h40s PET0 applicant's agent Patent attorney Takehiko Suzue 12- Figure 5 Vo. Procedural amendment 1981 1' [) Month 51.1 Mr. Kazuo Wakasugi, Commissioner of the Japan Patent Office■, Indication of the case Patent application No. 8-159312 No. 2 Name of the invention Semiconductor storage device 3, Name of the amendment with the Nagisa case Related: Patent applicant αm Tokyo Shibaura Electric Co., Ltd. 4, Agent address: 17 Mori Building 5, 1-26-5 Toranomon, Minato-ku, Tokyo, voluntary amendment 6, full text of the specification to be amended 7, description of the contents of the amendment Engraving (no changes to the content)

Claims (1)

[Claims] +11 A first word line divided into a plurality of lines, a plurality of bit lines arranged to intersect with these first word lines, and each of the first word line and bit line. A memory cell group divided into a plurality of sections provided corresponding to the intersection position, and a memory cell group of a plurality of sections each provided at one end of the plurality of first word lines and connected to the first word line. a selector consisting of a NOR gate for selection; second word lines each connected to one input end of the selector; a row decoder to which an address signal is supplied and selects the second word line in accordance with the address signal; 1. A semiconductor memory device characterized in that a section decoder is provided at the other input end of the royal selector for supplying a selection signal to section )' of a memory cell group. I2) 'The NOR gate constituting the selector is
The first and 21st JO8FETs of the first conductivity type and the third MOS FET of the second conductivity type are connected in series between the potential supply source and the second potential supply source, and the third λ-th MOS FET is connected in series between the potential supply source and the second potential supply source.
and a fourth MOS FET of a second conductivity type inserted between the connection point of
OS FET +7) gates are connected to the second word line, gates of the second and third MOS FETs are connected to a blind line to which the output of the section decoder is supplied, and the second and 31st JOEt FE'T 2. The semiconductor memory device according to claim 1, wherein the connection point ' is connected to the first word line.