JP2007059019A - Nonvolatile memory cell and storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To store data when powered off by providing an additional circuit in a nonvolatile storage circuit. <P>SOLUTION: The memory cell has: a pair of inverters constituted of a pair of field effect transistors and a pair of nonvolatile variable resistance elements connected to drain terminals of the transistors, and in which an input/output terminal is cross-coupled; and a power source supply line which is connected to the other end of the nonvolatile variable resistance element and to which control voltage is supplied. In the storage device, adjacent data can be stored when a memory cell is turned off by controlling the variable resistance element through the power source supply line. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention is a so-called non-volatile resistance in which a resistance value of a recording film is reversibly changed by applying voltages having different polarities to the two electrodes. A nonvolatile memory cell in which a nonvolatile function is added to the SRAM memory cell function by replacing the changeable storage element with a PMOS transistor of a six-transistor SRAM memory cell or by adding to the six-transistor SRAM memory cell, and The present invention relates to a storage device.

The 6-transistor type SRAM cell is widely used in memory products and logic products as one of the most common memory cells in a semiconductor, and is extremely excellent in terms of high-speed performance and stable operation. However, since the stored information is lost when the power is turned off, the memory cell cannot be used as it is for a nonvolatile memory.
On the other hand, flash memory is generally used as a non-volatile memory, but both NOR type and NAND type have a slow write / erase speed of 10 microseconds to 10 milliseconds, and the number of rewrites is limited to about 100,000 times. Therefore, even if it is suitable for data storage and file storage applications, it is difficult to say that it is a general-purpose nonvolatile memory.
Further, there is a memory in which SRAM and flash memory (EEPROM) are combined as a memory system combining different functions, and the SRAM information is saved in the flash memory when the power is turned off.
However, since the flash memory write / erase speed for saving data is as slow as 10 microseconds to 10 milliseconds, a system that frequently turns on / off power to reduce power consumption has operational problems. .
On the other hand, in logic circuits, flip-flop circuits are very commonly used as circuits for temporarily storing information, such as counters and shift registers. However, since the information is lost when the power is turned off, necessary data is stored in a non-volatile memory provided separately before the power is turned off.
Further, as an attempt to make the flip-flop circuit non-volatile, for example, there is an embodiment using an MRAM (Magnetoresistive Random Access Memory) as a non-volatile memory element, but the circuit becomes large (that is, the circuit area increases and the cost increases). Therefore, further ingenuity is necessary for practical use. This embodiment is disclosed in Patent Document 1, for example.
JP 2003-233990 A

  An object of the present invention is to provide a nonvolatile memory cell capable of random access and high-speed operation similar to an SRAM and a storage device using the nonvolatile memory cell.

The nonvolatile memory cell of the present invention is composed of a pair of field effect transistors and a pair of nonvolatile variable resistance elements connected to the drain terminals of the transistors, a pair of inverters whose input / output terminals are cross-coupled, A power supply line connected to the other end of the nonvolatile variable resistance element and supplied with a control voltage.
The memory device of the present invention includes a pair of field effect transistors and a pair of nonvolatile variable resistance elements connected to the drain terminals of the transistors, a pair of inverters whose input / output terminals are cross-coupled, and the nonvolatile memory A power supply line connected to the other end of the variable resistance element to which a control voltage is supplied, and a memory cell arranged in a matrix and a gate terminal of an access transistor of the memory cell are commonly connected in the row direction And a pair of bit lines commonly connecting the drain ends of the access transistors in the column direction, and one end of the variable resistance elements are commonly connected in the row direction in order to vary the characteristics of the variable resistance elements. A control circuit for supplying a control voltage to the power supply line.

  A nonvolatile memory device capable of random access and high-speed operation similar to SRAM can be obtained. Further, even if the power is turned off, the previous state can be stored, and after the power is turned on again, the state can be read and the operation can be continued.

The non-volatile storage device that can perform random access and high-speed operation similar to SRAM (Static Random Access Memory) will be referred to as non-volatile SRAM for convenience.
The nonvolatile SRAM using the present invention has the following operation methods.
First, a write / erase operation is performed on a nonvolatile variable resistance element (hereinafter also referred to as an ARAM element) each time data is written to a memory cell, and ARAM is read each time data is read from the memory cell. There is a method of performing a read operation from an element, and this method is hereinafter referred to as “type I” or “anytime write / anytime read operation type”.
Second, every time data is written to the memory cell, the ARAM element is written / erased. When data is read from the memory cell, the read ARAM element is read as an SRAM cell during the power-on period. There is a method of performing an operation used simply as a load of a memory cell and performing an operation of reading (transferring) data stored in an ARAM element to an SRAM cell only when power is turned on. This method is hereinafter referred to as “type II” or “ It will be referred to as “anytime write / power-on read operation type”.
Although both types have their own advantages and disadvantages, “Type I” is characterized by low power consumption (especially zero power consumption during standby) because the cell power supply can be completely shut down when the memory cell is not accessed. . On the other hand, “Type II” is characterized in that it operates as an SRAM cell during the power-on period, so that it can operate as fast as an SRAM.
Third, during the power-on period, a write / read operation is performed as an SRAM cell, and data stored in the SRAM cell is written (transferred) to the ARAM element immediately before the power is turned off, and stored in the ARAM element when the power is turned on. There is a method of reading (transferring) the data to the SRAM cell. Hereinafter, this method will be referred to as "type III" or "power-off write / power-on read operation type". This “type III” can operate at the same high speed as an SRAM, and can have low power consumption.
Hereinafter, the configuration of the memory cell and the nonvolatile memory device and the operation thereof will be described.

FIG. 1 shows a block configuration of a nonvolatile memory device 10 according to an embodiment.
The nonvolatile memory device 10 includes a word line driver circuit 20, a decoder / control circuit 30, a write buffer / sense amplifier circuit 50, and a memory cell MC unit. 40 or the like.
In Figure 1, for simplicity, although only one word line driver (Word Driver) circuit 20 and the memory block BLK1 not shown, the memory block (BLK1) is, for example, the word lines are arranged ^{2 3} units There are 2 ⁿ / 2 ³ (n is a positive integer and the number of row address bits).
In Figure 1, the word lines in the block (WBLK1～WBLKn) of the word line driver circuit 20 is present ^{2 3,} Yes illustrated with WLO to WL7, also the memory cells MC with respect to each of the word lines (lines) (41-00, 41-10,..., 41-70,...) Are connected.

The decoder / control circuit 30 includes a predecoder, an internal timing control circuit, and the like, and receives address data and decodes it. In addition, an internal clock signal, a control signal, etc. generated based on the external clock (CK) are also generated.
In order to reduce the number of transistors and reduce the area of the decoder (Decoder) circuit (30) and to operate at high speed, a predecoder system is generally used for the purpose of increasing the storage capacity, increasing the speed, and reducing the power consumption. ing.
In this pre-decoder method, when a multi-bit address is input, it is decoded (pre-decoded) into a plurality of groups of 2 bits or 3 bits, for example, and a specific group is selected from these groups. Within a group, one word line is selected from 2-bit or 3-bit word lines. Thereby, power consumption is reduced.
Also, if the number of bits in the selected decoder is reduced, the load on the address buffer can be reduced and the operation speed can be increased. On the other hand, if the number of bits in the decoder is increased, the wiring area can be reduced, but the load on the address buffer is reduced. Increases and the operating speed slows down. For this reason, the word lines in one block constituted by the word line driver circuit 20 often have 2 or 3 bit configurations as described above.
The decoder circuit (30) includes a column address decoder in addition to the row address decoder, and this column address decoder selects a column (column direction) address based on the input address data.
When the control signal (Control) and the clock CK signal are supplied from the outside, the timing control circuit of the control circuit (30) responds to, for example, the control signal (WE; write enable signal) and the predecoder and the word line driver circuit 20 Outputs a timing signal for decoding the address signals A [0] to A [n].
In addition, an internal clock (PCLK) is generated and a control signal (WE; write enable) signal is output to a write buffer circuit to control the write timing.
The control circuit (30) is provided with a power supply (PWR) line, PWR0 to PWR7 in the row direction in pairs with each word line, and is connected to one end of the nonvolatile variable resistance element of each memory cell MC. ing.

When a specific memory cell MC is selected, the power supply line is turned on / off during normal operation, or the voltage is increased at a predetermined timing before the power is turned on (ON), or the voltage is changed after the power is turned off (OFF). In other words, data is written, erased or read by controlling the voltage supplied to the variable resistance element.
The control circuit (30) outputs a sense amplifier enable signal to a sense amplifier (SenseAmp) circuit (50) that amplifies data on the bit line Bit and the inverted bit line XBit (inversion of Bit).
Further, a timing signal for controlling the column addresses [An + 1] to [Am] (data) output from the column decoder is also output.

One word line driver circuit 20 is selected by the predecoder, and the clock (PCLK) and data (DATA) output from the decoder / control circuit 30 are supplied to the selected specific word line driver circuit 20. .
In the selected block of the word line driver circuit 20, for example, when the unit of the decoder is 3 bits, an “H” (high) level voltage is supplied from 8 word lines to one word line. The row direction of the memory cells MC (41-0 to 41-7) is activated (activated). At the same time, the other seven word lines are supplied with an "L" (low) level voltage and are deactivated.
As shown in FIG. 1 as an example, the specific circuit configuration of each word line driver circuit 20 includes, for example, a NAND circuit and a NOT circuit, and the control signal clock and data output from the decoder / control circuit 30 are input to the NAND circuit. After being supplied and operated, the logical result is inverted by the NOT circuit and output to the word lines WL0 to WL7 that drive the memory cells MC (41-00, 41-10,...).
A voltage is supplied to the power supply lines (PWR0 to PWR7) corresponding to the activated word line at a predetermined timing, and data in the nonvolatile variable resistance element is erased, written or read.

The write buffer circuit constituting a part of the write buffer / sense amplifier circuit 50 is supplied with a write enable (WE) signal and a column selection signal from the column decoder, and when a specific column is selected, reading and writing of data are performed. Done.
At the time of reading, based on the signal from the internal timing control circuit, first, the data stored from the ARAM element is read and stored in the SRAM cell. Thereafter, the data of the selected memory cell MC is output onto the bit line pair Bit, XBit, this data is amplified by the sense amplifier circuit (50), and the data is passed through the output buffer of the write buffer / sense amplifier circuit 50. Output (Out).
On the other hand, at the time of writing, data is supplied to the write buffer / sense amplifier circuit 50 via the input terminal. When the bit line pair Bit, XBit selected by the column selection signal is selected, data is written into the memory cell MC via the write buffer circuit and the bit line pair Bit, XBit.
In order to store the data of the memory cell in the ARAM element when the power is turned off, the word line and the power supply line are controlled during the write cycle period to erase and write the data. In addition to this, when the power is turned on, the power supply line is controlled to start up earlier than other power supplies so that data can be read from the ARAM element.

In the memory cell (MC) section 40, for example, a plurality of memory cells MC41-00 to MC41-nm such as SRAM cells are arranged in a matrix, and generally MC41-00 to MC41-0m are connected to the same word line and power supply line. MC-00 to MC-n0 are commonly connected to a bit line pair Bit, XBit, and the bit line pair Bit, XBit is connected to a sense amplifier (50).
The example of the memory cell MC unit 40 in FIG. 1 shows only one column of the nonvolatile SRAM, and actually includes a plurality of columns.
The operation of the main part of the nonvolatile memory device 10 shown in FIG. 1 will be described later with reference to a circuit configuration of a memory cell and a timing chart.

The circuit configuration of the embodiment of the memory cell MC of the memory cell MC section 40 of FIG. 1 is shown in FIGS.
In the memory cell MC100 shown in FIG. 2, the drain of an NMOS (N-channel Metal Oxide Semiconductor) transistor 111 is connected to the drain / source of an NMOS transistor 113 as a transfer gate and one terminal of a variable resistance element 119, and the gate is connected to an NMOS transistor 112. And the source is connected to a reference voltage such as GND (ground).
The other terminal of the variable resistance element 119 is connected to a power supply (PWR) line 118. The gate of the NMOS transistor 113 is connected to the word line 117, and the source / drain is connected to the bit (bit) line 115.
Similarly, the drain of the NMOS transistor 112 is connected to the drain / source of the NMOS transistor 114 serving as the transfer gate and one terminal of the variable resistance element 120, the gate is connected to the drain of the NMOS transistor 111, and the source is connected to a reference voltage such as GND ( Ground).
The other terminal of the variable resistance element 120 is connected to the power supply line 118. The gate of the NMOS transistor 114 is connected to the word line 117, and the source / drain is connected to the XBit (inversion of the Bit line) line 116.
The operation of the memory cell MC100 will be described later.

FIG. 3 shows a circuit configuration of a memory cell MC150 which is another embodiment.
The memory cell MC150 shown in FIG. 3 includes P-channel MOS (Metal Oxide Semiconductor) transistors 155, 156, N-channel MOS transistors 151, 152, 153, 154, and variable resistance elements 161, 162.
The word line 159 is connected to the gates of the NMOS transistors 153 and 154 serving as transfer gates, and the bit (Bit) line 157 and the inverted bit (XBit) line 158 are connected to the drains / sources of the NMOS transistors 153 and 154.
The source of the PMOS transistor 155 is connected to the power supply, and the drain is connected to the drain of the NMOS transistor 151 and the source / drain of the NMOS transistor 153. The source of the NMOS transistor 151 is connected to a reference potential such as GND (ground).
Similarly, the source of the PMOS transistor 156 is connected to the power supply, and the drain is connected to the drain of the NMOS transistor 152 and the source / drain of the NMOS transistor 154. The source of the NMOS transistor 152 is connected to a reference potential such as GND (ground).
The gates of the PMOS transistor 155 and the NMOS transistor 151 are connected in common, and the commonly connected gate is connected to the commonly connected drains of the PMOS transistor 156 and the NMOS transistor 152.
The gates of the PMOS transistor 156 and the NMOS transistor 152 are connected in common, and the commonly connected gate is connected to the commonly connected drains of the PMOS transistor 155 and the NMOS transistor 151.
A variable resistance element 162 is connected between the commonly connected gate of the PMOS transistor 155 and the NMOS transistor 151 and the power supply line (PWR) 160, and between the commonly connected gate of the PMOS transistor 156 and the NMOS transistor 152 and the power supply line 160. Is connected to the variable resistance element 161.
In consideration of the polarity of the voltage supplied to the power supply line 160, by setting the high voltage and the low voltage, the resistance values of the variable resistance elements 161 and 162 can be varied to write, erase and read data. Is going.

Next, the operation of the memory cell MC100 will be described with reference to FIG. 2, FIG. 4, and FIG. FIG. 5 is a timing chart for explaining the operation of the memory cell MC100. FIG. 4 shows electrical characteristics (IV characteristics and RV characteristics) of the non-volatile variable resistance elements 119, 120, 161, and 162.
First, the write-on-time / power-on read operation type (type II) will be described.
In the initial state, the storage node 121 in the memory cell MC (100) has a high potential (also described as “H” level in the following description), and the storage node 122 has a low potential (also described as “L” level in the following description). ). At this time, the variable resistance element 119 is in a low resistance state, and the variable resistance element 120 is in a high resistance state.
Now, a case where opposite data is written to the memory cell MC100 will be described. During the write cycle, when the clock input is at “H” level, data is input (FIG. 5D).
Corresponding to the input data, the bit line 115 is set to a low potential (for example, ground potential) and the inverted bit (XBit) line 116 is set to a high potential (for example, a power supply potential) to set the word line 117 to “H”. Level voltage is supplied. When this “H” level voltage is supplied to the gates of the NMOS transistors 113 and 114 of the transfer gate, it becomes conductive (opens), and the “H” level voltage of the inverted bit (XBit) line becomes the NMOS transistor of the transfer gate. 114, the storage node 122 is set to the “H” level, and the voltage of the “H” level is supplied to the gate of the NMOS transistor 111 to be turned on.
The drain of the NMOS transistor 111 becomes “L” level, and the voltage of this “L” level is fed back and supplied to the gate of the NMOS transistor 112 to be turned off. As a result, the drain of the NMOS transistor 112 is held at the “H” level.
As shown in FIG. 5H, the potentials of the storage nodes 121 and 122 in the cell are inverted during the period 101, and transitions from “H” level to “L” level and “L” level to “H” level, respectively. To do.

  After that, if the potential of the power supply (PWR) line 118 is kept at the high potential for the period of 102 shown in FIG. 5 (FIG. 5E), the variable resistance element 119 has −Ve or more shown in FIG. Since a negative voltage is applied, the variable resistance element 119 changes from the low resistance state to the high resistance state. That is, the erasing operation of the variable resistance element 119 occurs during the period 102 shown in FIG.

Next, in FIG. 5E, when the power supply line 118 is lowered to a low potential and the state is maintained for the period 103 shown, a positive voltage equal to or higher than Vw shown in FIG. Therefore, the variable resistance element 120 changes from the high resistance state to the low resistance state. That is, the write operation of the variable resistance element 120 occurs.
After the power supply line 118 is returned to the high potential, the word line 117 is closed, the NMOS transistors 113 and 114 of the transfer gate are turned off, and the bit line 115 is returned to the high potential, thereby completing the write operation. .
In this state, the storage node 121 is at the “L” level, but the variable resistance element 119 connected to the power supply line 118 is in a high resistance state, so that no unnecessary current flows. Since the storage node 122 is at “H” level and is connected to the power supply line 118 by the variable resistance element 120 in a low resistance state, the potential of the storage node 122 is held at “H” level.

Next, the reading operation will be described. This read operation is the same as a normal SRAM read operation. The bit (Bit) line 115 and the inverted bit (XBit) line 116 are set to the “H” level, and the “H” level voltage is output to the word line 117.
When this “H” level voltage is supplied to the gates of the NMOS transistors 113 and 114 serving as transfer gates, the transistors are turned on, and the voltages of the storage nodes 121 and 122 are transferred to the bit line 115 and the inverted bit line 116.
Then, the potential of the bit line on one side slightly decreases according to the potentials of the storage nodes 121 and 122 of the memory cell MC150, and read data is output by detecting this minute potential difference with a sense amplifier (FIG. 5). (I), (J), (K)).
At this time, since the variable resistance element 120 on the “H” level side of the storage node (storage node 122 in FIG. 5) is in the low resistance state, the power supply potential (power supply line potential) is always on the “H” level side of the storage node. ) Is supplied. As described above, the variable resistance elements 119 and 120 function in the same manner as the PMOS load of the 6-transistor SRAM cell during the read operation.
Even when the power is turned off in this state, the resistance values of the variable resistance elements 119 and 120 are maintained as they are because they are nonvolatile (FIG. 6).

Next, as shown in FIG. 6, consider the case where data is read from the variable resistance (ARAM) element when the power is turned on (ON).
It is assumed that the variable resistance element 119 is in a high resistance state and the variable resistance element 120 is in a low resistance state when the power is turned off. When the power supply line 118 rises to a high potential prior to other power sources (period 104 shown in FIG. 6E), the potentials of the cell internal storage nodes 121 and 122 depend on the state of the variable resistance elements 119 and 120. Become “L” level and “H” level, respectively (FIGS. 6G and 6H).
When the “H” level voltage of the storage node 122 is supplied to the gate of the NMOS transistor 111, the ON operation state is established, and the drain becomes the “L” level.
The “L” level voltage of the drain of the NMOS transistor 111 is supplied to the gate of the NMOS transistor 112, but is in the OFF state.
That is, the voltage levels of the storage nodes 121 and 122 are stably maintained by the positive feedback of the driver NMOS transistors 111 and 112. Thereafter, the above-described write and read operations can be performed.

Next, description will be made on the operation of the occasional write / anytime read operation type (type I) using the memory cell MC100 shown in FIG.
FIG. 7 is a timing chart of the arbitrary write / optional read operation of the memory cell MC100 of the embodiment.
In the initial state, data is held in the variable resistance elements 119 and 120. For example, assume that the variable resistance element 119 is in a low resistance state and the variable resistance element 120 is in a high resistance state. It is assumed that the potential of the power supply line 118 is at “L” level and the storage nodes 121 and 122 in the memory cell MC are both at “L” level because the word line 117 is closed and sufficient time has passed.
Consider a case where opposite data is written to the memory cell MC100. As shown in FIG. 7A, when the clock input during the write cycle is at “H” level, the bit (Bit) line 115 is set to a low potential (for example, ground potential), and the inverted bit (XBit) line 116 is set. An “H” level voltage is supplied to the word line 117 at a high potential (for example, a power supply potential). Then, since this “H” level voltage is supplied to the gates of the NMOS transistors 113 and 114 of the transfer gate, they become conductive (open).
When the word line 117 is opened, the storage node 121 in the memory cell MC remains at the “L” level during the period 105 shown in FIGS. 7G and 7H, but the storage node 122 remains at the high potential (“ H ”level). At this time, if the potential of the power supply line 118 is changed to a high potential for the period 106 shown in FIG. 7E, a negative voltage of −Ve or higher is applied to the variable resistance element 119. It changes to a high resistance state (FIG. 4). That is, the erase operation of the variable resistance element 119 occurs.

Next, when the power supply line 118 is lowered to a low potential and the state where the word line 117 is opened for the period 107 shown in FIG. 7E is maintained (FIG. 7F), this time, the variable resistance element 120 has a voltage higher than Vw. Is applied, the state changes from a high resistance state to a low resistance state. That is, the write operation of the variable resistance element 120 occurs.
Thereafter, the word line 117 is changed from the “H” level to the “L” level, the NMOS transistors 113 and 114 of the transfer gate are closed (turned off), and the bit line 115 is returned to the high potential, thereby writing. The operation ends.
At this time, the variable resistance element 119 becomes high resistance and the variable resistance element 120 becomes low resistance, and this state is maintained. Although the storage node 122 is at a high potential when the word line 117 is closed, since the power supply line 118 is low and no power is supplied, the storage node 122 eventually settles to the ground potential due to a leak current inside the memory cell MC100.

Next, the read operation will be described with reference to FIG.
In the read cycle period of FIG. 7, first, when the power supply line 118 is raised to a high potential while the word line 117 is closed at the “L” level (period 108 shown in FIG. 7E), the variable resistance elements 119, Depending on the state of 120, the potentials of the cell internal storage nodes 121 and 122 become “L” level and “H” level, respectively, and this state is stably held by the positive feedback of the NMOS transistors 111 and 112.
Therefore, when the bit (Bit) line 115 and the inverted bit (XBit) line 116 are set to the “H” level to increase the potential of the word line 117, the NMOS transistors 113 and 114 of the transfer gate become conductive.
The potentials of the storage nodes 121 and 122 of the memory cell MC100 are transferred to the bit line 115 and the inverted bit line 116 through the transfer gate, and the bit line potential on one side slightly decreases according to the transferred potential difference. The read data is output by detecting the potential difference with the sense amplifier.
When the potential difference between the bit lines (Bit; 115, XBit; 116) is detected by the sense amplifier, the word line 117 is closed, and then the power supply line (118) is returned to the “L” level to complete the read operation. To do. The storage node (121, 122) potential in the memory cell eventually settles to the ground potential as in the write operation.
As described above, by using the present invention, a nonvolatile memory device capable of random access and high-speed operation similar to SRAM can be obtained.

Next, using the memory cell MC150 shown in FIG. 3, which is another embodiment, the memory cell operation of the write / power-on read operation type and the power-off write / power-on read operation type at any time will be described. To do.
First, in the memory cell MC150 shown in FIG. 3, the operation of the write operation / read-on operation type at any time will be described with reference to FIGS.
It is assumed that storage node 163 in memory cell MC (150) is in a high potential (“H” level) and storage node 164 is in a low potential (“L” level) in the initial state. At this time, the variable resistance element 161 is in a low resistance state, and the variable resistance element 162 is in a high resistance state.
Consider a case where opposite data is written to the memory cell MC150. When the bit (Bit) line 157 is set to a low potential (eg, ground potential) and the inverted bit (XBit) line 158 is set to a high potential (eg, power supply potential), an “H” level voltage is output to the word line 159. A voltage of “H” level is applied to the gates of the NMOS transistors 153 and 154 of the transfer gate, and as a result, they become conductive (open).
When an “H” level voltage is supplied to the common gate of the PMOS transistor 155 and the NMOS transistor 151 via the NMOS transistor 154 of the transfer gate, the NMOS transistor 151 is turned on and its drain output is “L”. Become a level. The “L” level of the drain output of the NMOS transistor 151 is fed back to the commonly connected gates of the PMOS transistor 156 and the NMOS transistor 152. As a result, the PMOS transistor 156 is turned on and the drain output becomes the “H” level.
As described above, the PMOS transistor 155 and the NMOS transistor 151 constitute a first inverter, and the PMOS transistor 156 and the NMOS transistor 152 constitute a second inverter, and the outputs are fed back to the inputs of the other inverter. Thus, a latch circuit is configured to hold data (voltage).
Accordingly, the potentials of the storage nodes 163 and 164 in the cell are inverted during the period 101 shown in FIGS. 8G and 8H, and the “H” level → “L” level and “L” level → “H” level, respectively. Transition to.
If the potential of the power supply line 160 is kept high for the period 102 shown in FIG. 8E, a negative voltage equal to or higher than −Ve shown in FIG. 4 is applied to both ends of the variable resistance element 161. The variable resistance element 161 changes from the low resistance state to the high resistance state. That is, the erase operation of the variable resistance element 161 occurs.

Next, when the power supply line 160 is lowered to a low potential and the state is maintained for the period 103 shown in FIG. 8E, a positive voltage equal to or higher than Vw shown in FIG. 4 is applied to both ends of the variable resistance element 162. Therefore, the variable resistance element 162 changes from the high resistance state to the low resistance state. That is, the write operation of the variable resistance element 162 occurs.
After the power supply line 160 is returned to the high potential, the word line 159 is closed and the bit line 157 is returned to the high potential, thereby completing the write operation. In this state, the storage node 163 is at the “L” level, but the variable resistance element 161 between the storage node 163 and the power supply line 160 is in a high resistance state, and therefore no unnecessary current flows.

Next, the read operation will be described with reference to FIG. This read operation is the same as a normal SRAM read operation.
When the bit line 157 and the inverted bit line 158 are set to the “H” level and the word line 159 is opened, the bit line potential on one side slightly decreases according to the potential of the storage nodes 163 and 164 of the memory cell MC150. Is detected by the sense amplifier, and read data is output (FIG. 8 (I), (J), (K)).
At this time, since the variable resistance element 162 on the “H” level side of the storage node (storage node 164 in FIG. 8) is in the low resistance state, the second power supply potential (power source) is always on the “H” level side of the storage node. (Supply line potential) is supplied, and operation stability (noise margin) is further increased as compared with a normal 6-transistor type SRAM cell.
As described above, the variable resistance elements 161 and 162 function in the same manner as the PMOS load of the 6-transistor SRAM cell during the read operation.
Even if the power is turned off in this state, the resistance values of the variable resistance elements 161 and 162 are non-volatile and are maintained as they are (FIGS. 9G and 9H).

Next, consider a case where the power is turned on (ON) as shown in FIG. It is assumed that the variable resistance element 161 is in a high resistance state and the variable resistance element 162 is in a low resistance state at the stage of power off (OFF).
When the power supply line 160 is raised to a high potential prior to other power sources (period 104 shown in FIG. 9E), the storage nodes 163 and 164 in the cell are changed according to the state of the variable resistance elements 161 and 162. The potentials become “L” level and “H” level, respectively, and this state is stably held by the positive feedback of the driver NMOS transistors 151 and 152. Thereafter, the above-described write and read operations can be performed.

Next, an operation of the write operation at power-off / read-on operation at power-on will be described using the memory cell MC150 shown in FIG.
FIG. 10 is a timing chart of the write operation at power-off and the read operation at power-on of the memory cell MC150 of the embodiment.
During the power-on period, the potential of the power supply line (160) is “H” level and the variable resistance elements 161 and 162 are both in a high resistance state, so the memory cell MC150 operates as a normal SRAM cell. In the state immediately before the power is turned off (OFF), it is assumed that the storage nodes 163 and 164 in the cell are at the potentials of “L” level and “H” level, respectively (FIGS. 10G and 10H).

Consider a case where data in storage nodes 163 and 164 in memory cell MC (150) is written (transferred) to a nonvolatile variable resistance element when power is turned off (OFF).
Before the power supply potential of the memory cell MC150 is turned ON, the potential of the power supply line (160) is lowered to the “L” level (ground potential), and the potential state is maintained for a period of 111 shown in FIG. At this time, since a positive voltage equal to or higher than Vw shown in FIG. 4 is applied to both ends of the variable resistance element 162, the variable resistance element 162 changes from the high resistance state to the low resistance state (the write operation of the variable resistance element 162 is performed). Occur).
Thereafter, even when the power is turned off, the resistance value of the variable resistance element is nonvolatile, so that the state (the variable resistance element 161 is in the high resistance state and the variable resistance element 162 is in the low resistance state) is maintained.

The read operation at power-on (ON) is exactly the same as the write-on-time / power-on read operation type described above.
That is, when the power supply line 160 rises to a high potential prior to other power sources (period 104 shown in FIG. 10E), the inside of the memory cell MC (150) depends on the state of the variable resistance elements 161 and 162. The potentials of the storage nodes 163 and 164 become “L” level and “H” level, respectively, and this state is stably held by the positive feedback of the driver NMOS transistors 151 and 152. Thereafter, the other power supply rises and normal writing and reading operations can be performed.
Thus, a nonvolatile memory device capable of random access and high-speed operation similar to SRAM can be obtained.

Next, FIG. 11 describes a nonvolatile flip-flop circuit using a nonvolatile variable resistance element, which is a specific circuit of the nonvolatile logic circuit 200 according to another embodiment.
The nonvolatile logic circuit 200 includes a volatile memory circuit 200A and an additional circuit 200B.
In the volatile memory circuit 200A, an input terminal In connected to normal logic is connected to one terminal of the switch 201, and the other terminal of the switch 201 is connected to the PMOS transistor 212 and the NMOS transistor 213 constituting the flip-flop circuit. The gates are connected in common and the drains connected in common to the PMOS transistor 210 and the NMOS transistor 211, respectively.
The commonly connected gates of the PMOS transistor 210 and the NMOS transistor 211 are connected to the commonly connected drains of the PMOS transistor 212 and the NMOS transistor 213.
The source of the PMOS transistor 210 is connected to the power supply, and the source of the NMOS transistor 211 is connected to the ground (GND).
The source of the PMOS transistor 212 is connected to the power supply, and the drain is connected to the drain of the NMOS transistor 213 and the input terminal of the switch 202. The source of the NMOS transistor 213 is connected to the ground.
The output of the switch 202 is connected to the output terminal Out, and is connected to a normal logic circuit.
Here, CMOS transistors are connected in parallel to the switches 201 and 202, and the clock CLK and the inverted clock XCLK are supplied to the gates, and ON / OFF control is performed.

The additional circuit 200B includes switches 203 and 204 and nonvolatile variable resistance elements 215 and 216. One end of the switch 203 is connected to the output of the switch 201 and the common drain connection point of the PMOS transistor 210 and the NMOS transistor 211. . The other end of the switch 203 is connected to one end of a variable resistance element 215, and the other end of the variable resistance element 215 is connected to a power supply (PWR) line 220.
One end of the switch 204 is connected to the input of the switch 202 and the common drain connection point of the PMOS transistor 212 and the NMOS transistor 213. The other end of the switch 204 is connected to one end of the variable resistance element 216, and the other end of the variable resistance element 216 is connected to the power supply line 220.

Next, the operation of the nonvolatile flip-flop (Flip / Flop) circuit of the nonvolatile logic circuit 200 will be described with reference to FIG.
As described so far, in the write-on-power-on / read-on-power-on operation type operation, even when data in the storage node in the SRAM cell is written to the nonvolatile variable resistance element, the storage node in the SRAM cell is nonvolatile. When data is read out from the variable resistance element, data is transferred between the pair of CMOS inverters and the pair of nonvolatile variable resistance elements while the word line is closed. Accordingly, the operation of the nonvolatile flip-flop circuit is the same as that described in the previous section.

In the volatile memory circuit 200A and the additional circuit 200B of the nonvolatile logic circuit 200 shown in FIG. 11, the switches 201 and 202 are switch circuits controlled by a clock for disconnecting the input / output terminals, and the switches 203 and 204 are nonvolatile. This is a switch circuit for disconnecting the variable resistance elements 215 and 216 from the normal flip-flop circuit (volatile memory circuit 200A).
During normal operation, in the volatile memory circuit 200A, the switches 201 and 202 are turned on and a logic signal is input from the input terminal In. For example, when the input logic is “H” level, it is input to the pair of inverter circuits via the switch 201. Then, an “H” level signal is supplied to the common gate of the PMOS transistor 212 and the NMOS transistor 213, so that the PMOS transistor 212 is turned off and the NMOS transistor 213 is turned on. Since the NMOS transistor 213 is in the ON operation state, the drain becomes “L” level, and this “L” level voltage is fed back to the commonly connected gates of the PMOS transistor 210 and the NMOS transistor 211. As a result, the PMOS transistor 210 is turned on and the NMOS transistor 211 is turned off. Since the PMOS transistor 210 is in the ON operation state, the drain is at the “H” level. Further, the “H” level voltage of the drain is fed back to the commonly connected gates of the PMOS transistor 212 and the NMOS transistor 213, and as a result, the NMOS transistor 213 maintains the ON operation state.
When CLK is at the “L” level and XCLK (inverted clock) is at the “H” level, the switch 202 is turned on, and the “L” level voltage at the drain connected in common to the PMOS transistor 212 and the NMOS transistor 213 is the output terminal Out. Is output from.
On the other hand, when the input logic level is “L” level, the above-described logic level is inverted, and the “H” level voltage is output from the output terminal Out to the normal logic circuit.

The volatile memory (flip-flop) circuit 200A can store data during a normal operation when the power is on, but cannot store data while the power is off. Therefore, by providing the volatile memory circuit 200A with the additional circuit 200B, data can be stored even when the power is turned off.
When the power supply other than the flip-flop circuit (200A) of the non-volatile logic circuit 200 is off, the switches 203 and 204 are turned on only when the power is turned on to turn on the flip-flop circuits (PMOS transistor 210, NMOS transistor 211 and PMOS transistor 212, Data is transferred between the NMOS transistor 213) and the nonvolatile variable resistance elements 215 and 216.
First, the write operation will be described. When the storage node N33 of the flip-flop circuit 200A is at "H" level and the storage node N34 is at "L" level, the variable resistance element 216 is erased along the path indicated by the dotted arrow 222 when the potential of the power supply line (220) is set high. When the potential of the power supply line (220) is lowered, the variable resistance element 215 is written through the path indicated by the dotted arrow 221 to reduce the resistance.

Next, the reading operation will be described. In a state where the power is off, first, the power supply (PWR) line 220 is turned on before other power sources. Following this, a voltage of “H” level is applied to the clock CLK and a voltage of “L” level to the inverted clock XCLK is applied to the gates of the switches 203 and 204 to make them conductive.
Before the power was turned off, the variable resistance element 215 was low resistance and the variable resistance element 216 was high resistance. Therefore, when the power supply line 220 rises, the storage node N33 is connected from the power supply line 220 via the variable resistance element 215 and the switch 203. Voltage is supplied. Since the variable resistance element 215 has a low resistance now, the high voltage of the power supply line 220 is supplied to the storage node N33 and becomes “H” level.
On the other hand, since the variable resistance element 216 has a high resistance, when the power supply line 220 rises, the storage node N34 is supplied with a voltage from the power supply line 220 via the variable resistance element 216 and the switch 204. However, since the “H” level voltage is supplied from the low resistance variable resistance element 215 to the gates of the PMOS transistor 212 and the NMOS transistor 213, the NMOS transistor 213 is turned on and the drain is set to the “L” level. .
The “L” level voltage at the drain of the NMOS transistor 213 is fed back to the common gate of the PMOS transistor 210 and the NMOS transistor 211, the PMOS transistor 210 is turned on, and the drain is at the “H” level.
As described above, the potentials of the storage nodes N33 and N34 in the volatile storage circuit 200A become the “H” level and the “L” level, respectively, according to the states of the variable resistance elements 215 and 216. The state of each of the nodes N33 and N34 is stably held by the positive feedback of 213. Thereafter, the other power supply rises and normal writing and reading operations can be performed.
During the normal operation period, the switches 203 and 204 are set to an off state, and the additional circuit 200B is disconnected from the flip-flop (volatile memory) circuit 200A so as not to affect the operation of the flip-flop circuit 200A.
FIG. 11 shows an example in which the switches 203 and 204 are used in the additional circuit 200B. However, there is no problem in operation even when the switches are directly connected without the switches and are always connected.
As described above, by providing an additional circuit having a switch and a nonvolatile variable resistance element in a normal flip-flop circuit, the voltage of the power supply line supplied to the variable resistance element can be controlled even when the power is turned off. The previous data is stored, read when the power is turned on, and transferred to the flip-flop circuit. For this reason, data can be stored even when the power is turned off.

Therefore, it is possible to obtain a nonvolatile memory cell capable of random access and a high-speed operation similar to an SRAM and a storage device using the nonvolatile memory cell.
In addition, a flip-flop circuit having a nonvolatile function is realized, and a nonvolatile logic circuit capable of storing a state immediately before turning off the power and continuing operation from the state after turning on the power again is obtained. Can do.

1 shows a configuration of a nonvolatile memory device according to an embodiment of the present invention. It is a circuit diagram of the non-volatile memory cell of the example of embodiment of this invention. It is a circuit diagram of the non-volatile memory cell of the example of embodiment of this invention. It is a figure which shows the characteristic of a non-volatile variable resistance. 3 is a timing chart for explaining a write operation and a read operation at power-on of the nonvolatile memory cell of FIG. 2 at any time. 3 is a timing chart for explaining a write operation and a read operation at power-on of the nonvolatile memory cell of FIG. 2 at any time. FIG. 3 is a timing chart for explaining write-in / read-out operations of the nonvolatile memory cell of FIG. 2 as needed. 4 is a timing chart for explaining a write operation and a power-on read operation at any time of the nonvolatile memory cell of FIG. 3. 4 is a timing chart for explaining a write operation and a power-on read operation at any time of the nonvolatile memory cell of FIG. 3. FIG. 4 is a timing chart for explaining a write operation at power-off and a read operation at power-on of the nonvolatile memory cell of FIG. 3. It is a figure which shows the structure of a non-volatile logic circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Nonvolatile memory device, 20 ... Word line driver circuit, 30 ... Decoder / control circuit, 40 ... Memory cell part, 50 ... Write buffer / sense amplifier circuit, 100, 150 ... Memory cell MC, 111, 112, 113, 114, 151, 152, 153, 154, 211, 213 ... NMOS transistors, 117, 159 ... word lines, 115, 157 ... bit (Bit) lines, 116, 158 ... inverted bit (XBit) lines, 118, 160 ... power supplies Supply (PWR) line, 119, 120, 161, 162, 215, 216 ... variable resistance element, 155, 156, 210, 212 ... PMOS transistor, 200 ... non-volatile logic (flip-flop) circuit, 200A ... volatile memory circuit , 200B ... additional circuit, 201, 202, 203, 204 ... switch Ji.

Claims (9)

A pair of field effect transistors and a pair of nonvolatile variable resistance elements connected to the drain terminals of the transistors, a pair of inverters whose input / output terminals are cross-coupled,
A memory cell having a power supply line connected to the other end of the nonvolatile variable resistance element and supplied with a control voltage.   2. The memory cell according to claim 1, wherein the nonvolatile variable resistance element is programmed or erased by applying voltages of different polarities across the variable resistance element. A pair of field effect transistors and a pair of nonvolatile variable resistance elements connected to the drain terminals of the transistors, a pair of inverters whose input / output terminals are cross-coupled, and the nonvolatile variable resistance elements A power supply line connected to an end and supplied with a control voltage, and a memory cell arranged in a matrix,
A word line commonly connecting the gate terminals of the access transistors of the memory cells in the row direction;
A pair of bit lines commonly connecting the drain ends of the access transistors in the column direction;
And a control circuit that supplies a control voltage to the power supply line in which one end of the variable resistance element is commonly connected in a row direction in order to vary the characteristics of the variable resistance element.   4. The storage device according to claim 3, wherein the nonvolatile variable resistance element is programmed or erased by applying voltages of different polarities across the variable resistance element.   The control circuit applies a pulsed first reference voltage to the power supply line only when a write operation, an erase operation, or a read operation is performed on the memory cell, and the write operation is performed on the memory cell. 4. The storage device according to claim 3, wherein the storage device is set to the second reference voltage in cases other than being performed.   When writing or erasing the nonvolatile variable resistance element in the memory cell, the control circuit sets the power supply line to a high potential while keeping the word line at a high potential and making the access transistor conductive. After erasing the nonvolatile variable resistance element information in the memory cell, the power supply line is lowered to a nonvolatile variable resistance element in the memory cell while the access transistor is kept conductive. When the read operation of the memory cell is performed, the word line is set to a low potential and the access transistor is closed, and the power supply line is set to a high potential to change the memory from the nonvolatile variable resistance element. The information is transferred to the cell storage node, and then the memory cell information is read by bringing the word line to a high potential and conducting the access transistor. Memory device according to claim 5, wherein the.   The control circuit applies a pulsed first reference voltage to the power supply line only when a write operation is performed on the memory cell, and a second reference voltage in a case other than when the write operation is performed on the memory cell. 4. The storage device according to claim 3, wherein the storage device is set to a voltage.   When writing or erasing the nonvolatile variable resistance element in the memory cell, the control circuit sets the power supply line to a high potential while keeping the word line at a high potential and making the access transistor conductive. After erasing the nonvolatile variable resistance element information in the memory cell, the power supply line is lowered to a nonvolatile variable resistance element in the memory cell while the access transistor is kept conductive. The storage device according to claim 7, wherein writing is performed. The control circuit changes the power supply line to a high potential prior to the power supply of the memory cell in a state where the access transistor of the memory cell is closed when power is turned on. 8. The storage device according to claim 7, wherein the stored information is transferred to a memory cell storage node.

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