JPS6049450A - Check system of back-up memory - Google Patents

Abstract

PURPOSE:To check the validity of data through a simple circuit by reading out the data on a prescribed address after a power supply is applied again to decide whether the data is valid or not and discriminating the validity of all data based on the result of said decision. CONSTITUTION:When a microprocessor 3 detects the second application of a power supply, the processor 3 reads the data on an address 1000 of an RAM5 to store it to a register A and also reads the data on an address 1001 of the RAM5 to store it to a register B after inversion. Then the processor 3 judges whether the data are equal to each other between registers A and B. If both data are equal to each other, it is decided that all data of RAM5 and 6 are valid. Then a main program is executed. In case no coincidence is obtained between both data, the data of the address 1000 is read and stored to the address 1001 after inversion to execute an initial start action. Therefore, the data of the RAM6 is supplied to a printer 9 when the coincidence is obtained from the results of comparison. While the processor 3 starts again its actuation from the first when the coincidence is not obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for testing the validity of data in a battery-backed memory used in a relatively simple microcomputer system or the like.

[Technical background of the invention and its problems]

2. Description of the Related Art In systems such as microcombiners, a memory that can be freely read and written is used as a storage area for necessary data. A semiconductor IC memory called RAM is known as a typical example of such a memory. This RAM has a characteristic that when the power is cut off, the data stored therein disappears. Of course, non-volatile RAM is also known today, but this non-volatile RAM has a small capacity, a limited number of writes, and is expensive, so its uses are limited, so it will not be considered here. I'll decide.

Therefore, in a system such as a microcombeater using R and AM as described above, the following two methods have been investigated so that the system can operate normally after a period of time has elapsed since the power was cut off.

First, a device for providing data to the RAM (usually a host computer) performs rewriting when the power is turned on again. The second method is to use a battery for the RAM to perform battery backup when the power is cut off.

However, according to the former method, the host computer etc. must monitor the status of the terminal even after data is sent.
This has the drawback of increasing the load on the host computer, etc.

In the latter method, the load on the host converter etc. does not increase, but it is necessary to check whether the data held by the backup power supply is correct after the power is turned on again. That is, depending on the relationship between the capacity of the backup power source and the power-off time, the data in the RAM may not be held correctly. In order to perform this confirmation, a parity pit is added to each word of write data, and a parity check is performed after the power is turned on again.

However, according to this method, for example, it is necessary to add one memory bit to the data in units of word r.
Because of this parity bit, the data was compressed by 1 bit υ, so it was necessary to have an extra data area of 1 bit.

Furthermore, adding a parity generator or the like for generating a parity bit to a relatively simple microconverter or the like has the drawback of increasing the amount of software and increasing the cost.

[Purpose of the invention]

The present invention has been made in view of the drawbacks of the conventional methods as described above, and its purpose is to suppress the increase in the load on host converters, etc. by adopting the above-mentioned second method, and to provide data data with a simple configuration. An object of the present invention is to provide a test method that can test the effectiveness of a test.

[Summary of the invention]

Therefore, the present invention provides a memory that is readable and writable and that is amplified by a battery pack when the power is turned off, and a predetermined tz? a writing means for writing data so that the data at the addresses of E have a specific relationship with each other; and a determination means for determining whether or not these data are valid based on the validity of the data, and the validity of all the data in the memory is determined based on the result of the determination by the determination means. achieved.

[Embodiments of the invention]

The present invention will be described in detail below with reference to the first page.

FIG. 1 is a diagram of a control system of a printer employing the method of the present invention. In the figure, 1 is a device E for transferring the sea urchin data, such as a host computer, paper tape reader, etc.
In the following, a host computer will be used as a representative. 2
shows an input interface connected to path 10,
Accept data transferred from the host computer 1. 3 indicates the microprocessor, F 1 in path 10
75 is used to control each section. Connected to the path 10 are a box OM4 in which a control program used by the microprocessor 3 is stored, and a box AM516. The RAM 5.6 is powered by the battery 7, and the data in the RAM 5.6 can be retained for a predetermined period of time even when the power is turned off. Further, an output interface 8 is connected to the Nomas 10, and a printer 9 is connected to the output interface 8.

In such a system, when data is transferred from the host computer l to the input interface 2,
Based on the control program in the microprocessor 3HROM4, data is received from the input interface 2 and stored in the AM6 via the node 10. In this example l
d, 几AM6#-t used as data buffer, I
1, AM5 shall be used as a working register. When the microprocessor 3 receives data to the effect that the Luko P has ended or detects that the RAM 6 has been filled with data (14), it notifies the input interface 2 that input is prohibited, and notifies the output interface 8 of the start of data output. , R, AM6 and transfers the data to the output interface 8 via the path 10. The printer 9 receives data from the output interface 8 and performs a printing operation based on this data.

Such microprocessor 3u, control f in ROMd
It has a backup memory inspection function based on the 11 zologram, and consists of functional units as shown in FIG. In the figure, a 21Fi writing means is shown, and this writing hand I221 writes data to a predetermined address in the RAM 5.6. Here, it is assumed that the entire memory area is shown in FIG. 3. In other words,
Address “0000” to address “0FFF” is stored in ROM4.

In the control program area, address “1ooo”
The area from address "IPFF" to address "IPFF" is a working memory area of RAM 5, and the area from address "2000" to address "FFFF" is a data/muffer area of RAM 6. In short, 1% AM5 consists of one IC, ICI, and RAM6 consists of three ICs ■C■
-Consists of engineering C1v. Here, the predetermined address is the address "1000", and the corner address is the address "1001".

Further, the data to be written may be data 2, which can only be considered to be an artificial addition to two adjacent addresses. For example, if data at address "1000" K8 (assuming 17YV of RAM 5.6 is 8 bits) is written transparently, write data that is congruent with the above data to the adjacent address "1001". Write. In addition, u to 7Y'Lisu"1001'
, 7PL/s "1000" It is also possible to write data obtained by rotating the written data to the right (or left).

In this embodiment, it is assumed that data at two shielded addresses is written in such a way that the data is complementary to each other. Here, the reason why the plurality of predetermined addresses are set as two addresses for hiding is as follows. In general, the spatial arrangement of memory and the address arrangement almost correspond. The probability that the data that is changed when the power is cut off becomes different from each other increases as the distance between the data increases spatially.

Therefore, if the addresses are discrete, even if the power is cut off and the data changes, there is a small chance that the data will still be different and have a specific relationship. On the other hand, if the address is a shield, the data will almost always change to the same data, and the S rate for maintaining the specific relationship given in advance will be even smaller than in the case of discrete addresses. . This is the reason mentioned above.

The writing means 21 writes data when the power is first turned on and when the power is turned on again, when it is determined that the data is not valid. Reference numeral 22 indicates a determining means, and in this embodiment, a power-on determining section 23. Reading section 24
．． It consists of register A, register B, and comparison section 25. The power-on determining section 23 outputs a power-on pulse 27 to the reading section when the voltage of the power source 26 changes from O to a predetermined voltage. The reading unit 24 reads the addresses '1000'' and '1001.
”, and when the power-on signal ξ 27 is received, the data at address “1000” is read out and stored in register A, and the data at address “1001” is read out and inverted and stored in register B. Compare. Part is register A
, H are taken in, compared to see if they match, and a judgment output 28 is output. When the determination output 28 indicates that there is a match, it is assumed that all the data of AM5.6 is valid, and the microprocessor v3 processes the main program. Further, when the judgment output path indicates that there is no match, the reading unit U receives the judgment output path, reads out the data at address "1000', inverts it, and stores it in the register B. At this time, the judgment output 28 is The writing means 21 that had received the data waits for the data to be stored in the register B, and then writes the stored data to the address "100".
When this process is completed, the microprocessor;
・The 3 initializes flags and performs an initial start operation.

FIG. 4 is a flowchart of a program when the above inspection is performed by the microprocessor 3. As shown in the figure, when the microprocessor 3 detects that the power has been turned on, it reads the data at address "1000" in RAM 5 and transfers it to register A, reads the data at address "1001" in RAM 5, inverts it, and transfers it to register B. Store in. Next, the microprocessor 3 determines whether the data in registers A and B are quiet (resultant), and if it is, it assumes that all data in l'LAMs 5 and 6 is valid and proceeds to execute the main block. . Also, when the data in register A and register B are not equal, I
Read the data at address “1000” of LAM5,
After inverting this, T(, AM5 address “1001
” and initializes the flags and executes the initial start operation.

Therefore, in the system shown in FIG. 1, the power is cut off during the operation of the printer 9, and then the battery is reinserted to carry out the above inspection. If the results of the comparison match, the data in the RAM 6 is subsequently input to the printer 9.

Furthermore, if they do not match, the microprocessor 3 will restart its operation from the beginning.

FIG. 5 is a flowchart for explaining another embodiment. In this embodiment, a plurality of sets of addresses are used to store data for inspection, and all data in the RAM is valid only when the data stored in all sets of addresses are congruent with each other. It is determined that . As a result, the number of inspection points becomes a plurality of fM points, which increases the reliability of the determination of effectiveness.

Figure z146 is the result of inspection 31 according to the example explained in the 5th old.
f indicates a memory map of a preferred memory. That is, R.O.
M4 and working register area 1) 7 bits'
The configuration of fLAM5 is the same as that shown in Fig. 3, but there are multiple data buffer areas such as BUF - BUFO, and the ICs that make up these areas are
An example of multiple cases such as ~IC■ is shown.

In such a case, it is better to use multiple sets of addresses (in this example, five sets) to store the data for inspection and perform the inspection on both the working register area and the data buffer area. Reliability increases. Furthermore, as shown in the figure, the set of addresses for storing data is Arjn, x, ADnx + 1
, ADR2, ADR2'+ 1,...

AI) Different ICs as shown in R,5,ADR5+1
By placing it at the Tetsuo address, even more reliable testing can be performed.

In the example, the data in one address was inverted and stored in the other address, assuming that the existence of two pieces of concomitant data in shielded addresses is impossible except for artificially. In order to increase reliability, predetermined data (for example, 10101010, etc.) may be prepared in advance and stored in one address, and inverted and stored in the other address. The storage address of the advanced test data shall not be used for storing normal data.

〔Effect of the invention〕

As explained above, according to the present invention, /? Since the data in the memory is retained by data backup, the load on the host converter etc. is not increased. Furthermore, a bar configuration such as a parity generator is unnecessary and simple. Furthermore, compared to the non-criteria check method, this method is convenient because it can reduce the proportion of data areas that cannot be used for inspection. In addition, with the Nozority check method (
However, this method does not have such limitations and is relatively reliable.

Therefore, it is particularly suitable for a system backed up by a small-capacity battery such as a capacitor because it is economical and reliable. It is also effective as a countermeasure against power outages that occur when the operator is absent.

[Brief explanation of the drawing]

Figure 1 shows the system of a printer that adopts the method of the present invention. 2.1 is a block diagram of an embodiment of the method of the present invention; FIG. 3 is a diagram showing a memory map of the memory inspected by the present invention; FIG. 4 is an implementation of the method of the present invention. FIG. 5 is a diagram showing a flowchart for explaining another embodiment of the method of the present invention, and FIG. 6 is a diagram showing a flowchart for explaining another embodiment of the method of the present invention. FIG. 3 is a diagram showing a memory map. 4...RC) M5,6...-RAM 7...Battery 21...Writing means 22...Judgment means 23.
...Power-on judgment section 24...Reading section 25...Comparison section agent Patent attorney Noriyuki Chika (and one other person) Fig. 1 Fig. 2 Fig. 4 Fig. 5

Claims (3)

[Claims] (1) A memory that is readable and writable and is backed up by a battery when the power is turned off, a writing means that writes data so that data at a plurality of predetermined addresses in the memory have a specific relationship with each other, and a power supply that is turned on again. determination means for later reading data stored at the plurality of predetermined addresses and determining whether or not the data is valid based on the data, and based on the determination result by the determination means. A backup memory inspection method characterized by determining the validity of all data in the memory. (2) The writing means writes data such that the data at the predetermined address and the address next to it become mutually congruent data, and the determining means inverts one of the read data to determine whether it matches the other data. The backup memory inspection method according to claim 1, wherein it is determined whether the data is valid or not by comparing whether the data is valid or not. (3) The writing means writes data to at least one of a plurality of predetermined addresses and an address thereof, and the determination means reads data written to the plurality of predetermined addresses and an address thereof. , Claim No. 1 is characterized in that it is determined whether or not data is valid for a set of data read from a shielded address.
) or (2).