JPS6049388B2 - Signal conversion method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal conversion method used for data transmission, etc., and in particular to a signal conversion method that performs binary to four-value conversion after A/D conversion of an analog signal. The present invention also provides a signal conversion method that ensures bit synchronization.

In the case of digital transmission, the demodulator usually requires a bit synchronization signal. However, during periods when there is no input analog signal, the output of a converter such as a delta modulator is
As shown in Figure A, the signal becomes a repeating signal of 0 and 1. To convert this signal from binary to quaternary, 2 bits are treated as 1 dibit, and the conversion shown in the table below can be performed in units of dibit. However, the binary to quaternary conversion value during the period when there is no input analog signal is , as shown in FIG. 32, becomes (+1), and the bit synchronization signal cannot be reproduced from this signal. In order to eliminate the above-mentioned drawbacks, the present invention proposes to reduce the clock frequency by 2.
After modulating with a rectangular wave having a frequency of 1/2, binary-to-quaternary conversion is performed, and bit synchronization is possible even during a no-signal period of the input analog signal. This will be explained below along with examples. In FIG. 1, 1 is an analog signal input terminal, 2 is an A/D conversion circuit such as a delta modulator, 3 is a clock signal input terminal, 4 is a flip-flop, 5 is an exclusive OR circuit, and 6 is a binary - In the four-value conversion circuit, 7 is an output terminal. Next, the operation will be explained.

The analog signal applied to the input terminal is applied to the A/D conversion circuit 2, and converted into the digital signal shown in FIG. 3A in accordance with the clock signal. This digital signal is applied to the exclusive OR circuit 5, and is calculated by the signal shown in FIG. 3, which is a frequency-divided clock signal by the flip-flop 4, to obtain the signal shown in FIG. 3C. This signal is applied to the conversion circuit 6, converted into the signal shown in FIG. 3E, and outputted from the output terminal. That is, unlike the conventional output waveform shown in FIG. 3-2, it becomes a signal that can detect a bit synchronization signal. FIG. 2 shows the configuration of the demodulator. 11 is a terminal to which a modulated input signal is applied, 12 is a Fuchinami circuit, 13 is a comparator, 14 is a bit synchronized regeneration circuit including a full-wave rectifier circuit, 15 is a 4-value to binary conversion circuit, 16
1 is a flip-flop, 17 is an exclusive OR circuit, 18 is a demodulation circuit for performing delta demodulation, etc., and 19 is an analog signal output terminal.

Figure 4 shows the signal waveform of the main part, A is the input terminal 1
1 is the output of the bit synchronization reproducing circuit, C is the output of the flip-flop, 2 and 2 are the outputs of the conversion circuit 15, and H and G are the outputs of the exclusive OR circuit 17. The operation of this demodulator will be explained.

The signal applied to the input terminal 11 has unnecessary components removed by the wave circuit 12 and is applied to the comparator 13 and the bit synchronization regeneration circuit 14. The synchronization signal reproduced by the bit synchronization reproduction circuit 14 is applied to the comparator 13, and synchronization is established to identify four-valued values. This identified signal is 4
5 is added to the value-to-binary conversion circuit 15 and converted into a binary signal. This binary signal is applied to an exclusive OR circuit 17 together with a bit synchronization signal frequency-divided by a flip-flop 16, and a delta-modulated signal is extracted. This delta modulated signal is applied to a demodulation circuit 18 and demodulated into an analog signal signal. Note that in this demodulator, the output of the exclusive OR circuit 17 is the fourth one depending on the state of the flip-flop 16.
Two situations occur as shown in Figures E and V.

However, the phase of the analog output corresponding to this is π(R
ad). For this reason, no effect occurs when a signal such as voice is targeted. Note that although only the baseband circuit configuration is shown in Figures 1 and 2, the digital output in Figure 1 and the
RF modulators such as AM, PM, and FM are generally inserted between the digital inputs in the figure.

As described above, according to the present invention, since modulation is applied at 1/2 of the clock frequency before binary-to-quaternary conversion, the level of the modulated output changes every dibit.

Therefore, synchronization can be easily achieved on the demodulator side. Furthermore, since the present invention does not require a frame signal for operating the transmitting side and the receiving side in the same phase, it has the advantage that bit synchronization can be achieved reliably even when there are many line errors.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a modulator to which the signal conversion method according to the present invention is applied, FIG. 2 is a block diagram of the demodulator, and FIGS. 3 and 4 are signal waveform diagrams, respectively. 2...A/D conversion circuit, 4...Flip-flop, 5...Exclusive OR circuit, 6...
- 2-value to 4-value conversion circuit.

Claims (1)

[Claims] 1 A/D converting the input analog signal to obtain a digital signal that repeats 0 and 1 during the period when there is no input analog signal, and converting this digital signal into 2 of this digital signal.
It modulates with a rectangular wave with a frequency of 1/2, and converts it into a signal that repeats 01, 10 for periods when there is no input analog signal, and then converts this modulated signal into a signal that repeats 00, 01, 1.
A signal conversion method characterized by converting 0 and 11 into four different values.