JPS604925B2 - Phase discrimination/counting circuit in displacement measurement equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase discrimination/counting circuit in a two-phase pulse conversion type displacement measuring device.

Recently, mechanical displacement (position) measuring devices have been developed that use detectors such as optical scales and magnetic scales based on Moire fringes, or rotary encoders.

This type of detector has two output terminals, and a pulse signal with a number of cycles corresponding to the amount of movement of the movable part is emitted from both output terminals, and both output signals have a phase difference of 90 degrees. Depending on the moving direction (positive or negative) of the movable part, which output phase advances is determined. Therefore, as a displacement measuring device, the phase of the output signal of the detector is advanced to determine the moving direction of the movable part, and depending on the moving direction, the output pulses are cumulatively (up-counted) or cumulatively decremented. (down-counting), and thereby the amount of displacement or position of the movable part can be digitally displayed. It is an object of the present invention to enable the phase discrimination/counting circuit in the above-mentioned displacement measuring device to be composed entirely of CMOS transistors, and in particular, to
The circuit configuration is such that a desired operation can be obtained using a C-MOS up/down counter equipped with a switching terminal for switching between up mode and down mode.

This provides an excellent phase discrimination/counting circuit that has a simple circuit configuration with a small number of elements, consumes little power, and is resistant to disturbances/disturbances. Hereinafter, one embodiment of the present invention will be described in detail based on the drawings.

Reference numeral 1 denotes a detector such as the above-mentioned optical scale, magnetic scale, or rotary encoder, and the movable part of this detector 1 is connected to a feed table of a machine tool or the like that is to perform position measurement.

When the movable part moves, a pulse signal with a number of cycles corresponding to the amount of movement is sent to the two output terminals A of the detector 1.
, B, respectively, and when the movable part moves in the positive direction, signal A has a phase lead of 90 degrees relative to signal B', and when the movable part moves in the negative direction, signal B becomes the signal. The phase advances by 90 degrees with respect to A. D flip-flop FF
, and FF2, logic gates G, and G2 are detector 1
The circuit is configured to generate a waveform obtained by differentiating the rising edge and falling edge of the output signal A.

D flip-flop FF, FF2 (hereinafter simply FF)
FF2) is the clock pulse CK from the oscillator 2,
FF is set when signal A is "H" (high level), and reset when signal A is "L" (low level), and FF2 is read from the D input at the rising edge of FF. , is set and reset with a delay of one cycle of clock pulse CK. Therefore, as shown in FIG. 2, the output A' of the logic gate ○, for which the logical product [Q,×Q2] is calculated, is a pulse signal with a width of one period of the clock pulse CK at the rising edge of the signal A. The output A' of logic gate ○2, for which the logical product [Q, x Q2] is calculated, has a waveform that emits a pulse signal with a width of one period of the clock pulse CK at the rising edge of signal A. . The D flip-flops FF3 and FF4 and the logic gates G3 and ◯4 are configured in the same manner as described above so as to create a waveform obtained by differentiating the rising and falling edges of the output signal B of the detector 1.

That is, as shown in FIG. 2, the output 8 of logic gate G3
is a waveform that emits a pulse signal with a width of one period of clock pulse CK at the rising edge of signal B, and the output B' of logic gate G4 emits a pulse signal with a width of one period of clock pulse CK at the falling edge of signal B. This is a waveform that emits a pulse signal with a certain width. Output A', A' of each logic gate G, ~G4
, B', B' are input to the logic gate G5, and their logical sum [A'+A'+B+B'], that is, the signal A or B
A pulse signal generated at a period of 1/4 of the logic gate G5
is output from.

Also, in logic gate ○6, as is clear from the figure,
A logical value of [Q,×B′+Qi×B+Q3×+Q3×A′] is obtained.

Therefore, the output of logic gate G6 generates a periodic pulse signal of i'4 of signal A or B only when the phase of signal A leads signal B by 90 degrees. Similarly, in logic gate G7, [Q, ×B'+Q・×B'+
A logical value of Q3×A'+Q3×A'] is obtained.

Therefore, as for the output of logic gate G7, a pulse signal having a period of 1/4 of signal A or B is generated only when the phase of signal B leads signal A by 90 degrees. A frequency divider 3 generates a clock pulse C& by dividing the clock pulse CK by 1/2. The output of the logic gate G5 is ANDed with the clock pulses CK and CK2 in the logic gate G3, and the output of the logic gate G6 is
The output of the above logic gate G7 is sent to the logic gate G9.
The outputs of are ANDed with clock pulses CK and CK2 in logic gates G and o, respectively. That is, when the movable part of the detector 1 moves in the positive direction, a pulse signal with a width of 1/4 period of the cook pulse CK is sent from the logic gates G3 and Go with a period of 1/4 of the signal A or B. is output. Note that the pulse output of logic gate G8 is higher than the clock pulse CK,
occurs with a delay of 1/4 period. Conversely, when the movable part of the detector 1 moves in the negative direction, the logic gate G8 and ○,
. , a pulse signal having a width of 1/4 period of the clock pulse CK is output at a period of 1/4 of the signal A or B. In this case as well, the pulse output of logic gate G8 is higher than the pulse output of logic gate G,o by clock pulse CK,
This occurs with a delay of 1'4 periods. The output of the logic gate G9 is supplied to the S input of the RS flip-flop FF5 to set it, and the output of the logic gate ◯, o is supplied to the R input of this FF5 to reset it.
The set output signal of the FF 5 is supplied to the mode switching terminal a of the counter 4, and specifies the operation mode of the counter 4.
Counter 4 is in up mode when input a is "H" and counts up the pulses supplied to counting input terminal b, and is in down mode when input a is "L" and counts up the pulses supplied to input terminal b. count down. This input terminal b receives the pulse signal output from logic gate ○8, which is connected to logic gates ○, . Supplied via. MM and MM2 are monostable multipipulators (hereinafter simply referred to as MM, MM2) with falling operation and rising operation, respectively, and the set output Q5 of FF5 changes from "H" to "
Immediately after switching from "L" to "H", the logic gates G, . is inhibited for a certain period of time, and the first pulse output from logic gate ○8 is prevented from being supplied to counter 4 after this cutoff.

In other words, the output of MM is always "H", and the output of Q
It operates when MM2 falls from "H" to "L", and its output becomes "L" for a certain period of time (slightly longer than 1/4 cycle of clock pulse CK), and similarly, the output of MM2 is always "
It operates when Q5 rises from "L" to "H" and its output becomes "L" for a certain period of time. As is clear from the above explanation, while the movable part of the detector 1 is moving in the positive direction, FF5 is set and the counter 4 is in the up mode, and the counting pulse from the logic gate G8 is Logic gate G, . It is supplied to the counter 4 via the counter 4 and is counted up.

When the moving direction of the movable part is reversed and becomes negative, F
F5 is reset and counter 4 goes into down mode, and the first counting pulse immediately after this switching is applied to logic gates G, .
After that, the counter is sequentially down-counted from the above count value. Therefore, the counter counts of the intervening pulses A', A', B', and B' corresponding to the position signals of the movable parts are as follows:
One-to-one correspondence can be maintained without deviation even when switching modes. The same applies when the movable part is switched from the negative direction to the positive direction. In this way, the amount of displacement (position) of the movable part accurately corresponds to the count value of the counter 4. As explained above, the phase discrimination/counting circuit in the displacement measuring device according to the present invention is a first circuit that obtains a waveform obtained by differentiating the rising edge and falling edge of both output signals from the two output terminals of the detector. and a second circuit that determines which of the two output signals is leading in phase by a logical operation of the two output signals and each output signal of the first circuit, and an up mode and a down mode. It has an up/down counter having a switching terminal for switching and a counting pulse input terminal, and supplies an output signal of the second circuit to a mode switching terminal of the counter, and also supplies an OR signal of each output signal of the first circuit. is supplied to the outside of the counter via the gate, and furthermore, the gate is inhibited for a certain period of time in response to the rising and falling edges of the output signal of the second circuit, and the first output signal immediately after the mode switching of the counter is Since the third circuit is provided to prevent the counted pulses from being input to the counter, all of the circuits can be constructed using C-MOSC, and in particular, a C-MOSC of the type having a mode switching terminal is provided. M.O.
Using the up/down counter based on S, it is possible to obtain the desired operation as a displacement measuring device.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG. 2 is a waveform diagram of each part in this circuit. 1...detector, 2...oscillator, 3...
...Frequency divider, 4"""force counter.

Claims (1)

[Claims] 1. In a displacement measuring device using a detector that emits pulse signals with a phase difference of 90 degrees from two output terminals at a cycle number corresponding to the amount of movement of the movable part, the output from the two output terminals of the detector is A first circuit obtains a waveform obtained by differentiating the rising edge and falling edge of both output signals, and a logical operation of the above two output signals and each output signal of the above first circuit is performed to determine which of the above two output signals. It has a second circuit that determines whether the phase is leading or not, and an up-down counter that has a switching terminal that switches between up mode and down mode and a counting pulse input terminal, and the output signal of the second circuit is connected to the mode of the counter. At the same time, the OR signal of each output signal of the first circuit is supplied to the counting pulse input terminal of the counter via a gate, and the rising edge and rising edge of the output signal of the second circuit are supplied to the counting pulse input terminal of the counter. Phase in a displacement measuring device comprising a third circuit that inhibits the gate for a certain period of time in response to a falling edge, and prevents the first counting pulse immediately after mode switching of the counter from being input to the counter. Discrimination/counting circuit.