JPS6048837B2 - Sense amplifier input voltage control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sense amplifier input voltage control circuit that suppresses the voltage amplitude of an input signal level to a sense amplifier circuit for a ROM that has a large capacity and is excellent in high speed.

In recent years, memories have become increasingly larger in capacity and higher in performance, and ROM-related devices such as mask ROM (ROM) and PROM (mask ROM) are no exception.

Currently, 128-bit or 256-bit level ROMs are being put into practical use, but as the capacity of ROMs increases, the sense that controls and amplifies the signals from the memory matrix becomes particularly important. This is a problem related to improving the characteristics of the amplifier. FIG. 1 is a conceptual diagram of a connection between a conventional memory matrix and a sense amplifier, and FIG. 2 is a specific circuit diagram thereof.

In both FIG. 1 and FIG. 2, the memory matrix 1 is an iXj memory store consisting of i rows of X lines and j columns of Y lines. The row lines X, ~Xi are input to the gates of i transistors from transistors Q, ~Qj, to Q, j-Qij, respectively, and the column lines Y, ~Yj are input to the gates of i transistors Q11~Qfl, respectively. Or transistor Qlj
It is input to the gates of j transistors from transfer transistors QIM to QjM to the connection point of drains J of -Qij.

In addition, the transistor Q1 is the transistor Q1M to QjM
This is a decoupling transistor for a load with respect to the connection point P between the drains of , and its gate and drain are connected to the connection point P.

On the other hand, the sense amplifier circuit 2 is composed of transistors Q2 to Q.

and Q. performs a level shift of the voltage to the node P, (which becomes the input point of the sense amplifier circuit 2), and transistors α and Q5 act as an inverter to amplify the level-shifted voltage, and the input level of the node P, The amplification level suitable for this is output to point P2. now,
In memory matrix 1, Xi row line and Yj
column line is selected and the voltage level of Xi) Yj rises and the voltages of the other row and column lines are at a low level, then
j is selected and becomes conductive.

In the memory matrix 1 with the IXj configuration, ROM information is determined to be "1" or "O" depending on whether the transistor Qij exists or not. If it is "1" information, the connection point P, is a transistor QiM
Since it is grounded through the transistor Qij, it becomes a low level, and the sense amplifier circuit 2 outputs a high level to the point P2.

On the other hand, if it is "O" information, for example, the transistor QjM
Even if becomes conductive, since transistors Q and j do not exist,
The connection point P1 is kept at a high level, and the sense amplifier circuit 2 outputs a low level at a point P2.

FIG. 3 shows the cell voltage characteristics in the circuit example of FIG. 2, that is, the transient characteristics of the potential at the connection point P between power supply voltages of 6V and 4V. Generally, the input/output characteristics of the sense amplifier circuit 2 are shown as shown in FIG. 4, and the point P2
Assuming that the input voltage at which the output voltage changes at the node P, that is, the voltage at the node P, is the sense level Vs, as shown in FIG. In the conventional circuit shown in FIG. 2, even after the voltage at the node P1 of the sense amplifier circuit 2 has passed the sense level Vs and the output logic level at the point P2 has been determined, the potential at the node P1 becomes lower. Attempts to change to a higher or lower potential level. Therefore, the connection point P1
Since the voltage amplitude level at is large, transient characteristics are poor when reading information opposite to the previous one, and there are drawbacks in that the read speed depends more than the power supply voltage. Up to now, several methods have been proposed to solve the above problems. A typical example is one in which an input voltage control circuit is provided between the memory matrix 1 and the sense amplifier circuit 2, but each of these circuits has a large number of elements and is complex. The present invention was made to eliminate the above-mentioned drawbacks of the conventional technology, and has a simpler circuit configuration, less voltage dependence, excellent high-speed performance, and a ROM. It is an object of the present invention to provide a sense amplifier input voltage control circuit suitable for a sense amplifier for use in the present invention.

Embodiments of the sense amplifier input voltage control circuit of the present invention will be described below with reference to the drawings.

FIG. 5 is a circuit diagram showing the configuration of one embodiment. In FIG. 5, the same parts as in FIG. 1 will be described with the same reference numerals. In FIG. 5, an input voltage control circuit 3 is provided between a memory matrix 1 and a sense amplifier circuit 2. In FIG.

This input voltage control circuit 3 includes transistors Q, 2 to Q,
. The gate of the transistor Q,2 is connected to the connection point P1 between the memory matrix 1 and the depletion transistor Q1 for load, and the power supply voltage is applied to the drain. It's getting old. Furthermore, the source is connected to the matching point P3 with the gate of the transistor Ql3, and the source is connected to the point P3 that matches the gate of the transistor
connected to the input end of the A power supply voltage is applied to the drain of the transistor Ql3.

The source of transistor Ql3 is connected to the gate of transistor Ql4. The drain of the transistor Ql4 is connected to the node P, and the source is grounded. Next, the operation of the sense amplifier input voltage control circuit of the present invention configured as described above will be explained.

FIG. 6 is a diagram showing the cell voltage characteristics in the embodiment of FIG. 5, that is, the transient characteristics of the potential at the connection point P between power supply voltages of 6V and 4V. Now, if a certain memory cell in the memory matrix 1 is selected and "O" information is read out, the potential at the node P increases and becomes a high level.

At this time, when the potential at the connection point P, exceeds the sense level Vs and attempts to rise in the horizontal layer, the gate potential of the transistor Ql2 is raised, the transistor Q,2 is turned on, and as a result, the gate of the transistor Q,3 is turned on. The potential rises and similarly, transistor Q,. is turned on, and the gate potential of transistor Q,4 also rises. is also turned on. At this time, the connection point P, is the transistor Q,.

Since it is grounded through, when the potential of the connection point P, tries to rise in the solar layer, the impedance of the transistor Q,, decreases and tries to lower the potential of the connection point P, in the solar layer, causing feedback. Take, Z connection point P,
The high level of will settle down to a certain value. According to FIG. 6, when the power supply voltage is 6V, the high level is 4.4V, and when the power supply voltage is 4V, the high level is 4V. On the other hand, when the content of the memory cell is "1" information, the potential at the J junction point P, decreases to a low level, but when the potential at the junction point P, exceeds the sense level Vs and further decreases, the transistor The gate voltage of transistor Q,2 also decreases, and as a result, the gate voltage of transistor Q,3 also decreases, and similarly transistors Q,
Since the gate voltage of transistor Q4 also decreases, transistor Q,.

is in the off state. At this time, since the high level at the connection point P, before reading out the "1" information, is suppressed to a certain level by the input voltage control circuit 3,
．． The cell voltage characteristics (computer simulation results) in FIG. 6 also show that the time taken to reach the sense level Vs is significantly improved.

As explained above, in the first embodiment shown in FIG.
By the input voltage control circuit 3 provided between the memory cell matrix 1 and the sense amplifier circuit 2, the connection points P,
Since the voltage amplitude level of is reduced, transient characteristics when reading reverse information are improved, and power supply voltage dependence is also significantly improved. Furthermore, the input voltage control circuit 3 is composed of a feedback circuit consisting of only three transistors Ql2 to Ql4, and has the advantage of being an input voltage control circuit for sense amplifier circuits for ROMs, which will become larger in capacity and faster in the future.

In the embodiment shown in FIG. 5, a depletion transistor Q for the load and a transistor Q in the input voltage control circuit 3 are used.

As a result, a DC bus is created between the power supply voltage and ground. If the purpose is not to reduce the power consumption of the solar layer (if the purpose is to reduce the power consumption of the transistors Q12 and Q,3, as in the second embodiment of the present invention shown in FIG. A switch transistor Q, between.

and the source of transistor Q,3 and transistor Q,. A switch transistor Ql6 can be provided between the connection point with the gate of and the ground.
A control signal φ is applied to the gate of this transistor Ql5.
It is also possible to create an input voltage control circuit with a standby function for low power consumption or an input voltage control circuit using a synchronous method by inputting the control signal φ' to the gates of transistors Q and 6. .

As described above, according to the sense amplifier input voltage control circuit of the present invention, the input voltage control circuit is provided between the memory storage section and the sense amplifier circuit, and a predetermined memory cell in the memory matrix is selected and the logic When reading out "O" information, if it exceeds the sense level, the potential at the connection point between the memory storage section and the load depletion transistor is lowered.
Feedback is applied to lower the voltage to a predetermined level, and when the memory cell reads logic "1" information and the potential at this connection point falls below the sense voltage, feedback is applied to raise the voltage to a predetermined level. With a simple configuration, the voltage amplitude of the input signal level to the sense amplifier circuit can be suppressed, and an input voltage control circuit with good transient characteristics that is less dependent on the power supply voltage can be realized.

Along with this, it has the advantage that it can be applied not only to large-capacity ROMs but also to all memory logic LSIs. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing the concept of connection between a conventional memory matrix and a sense amplifier circuit, FIG. 2 is a circuit diagram showing a specific connection relationship between a conventional memory matrix and a sense amplifier circuit, and FIG. The figure is a cell voltage characteristic diagram of the memory cells in the memory matrix in Figure 2,
4 is a diagram showing the input/output characteristics of the five sense amplifier circuits in FIG. 2, FIG. 5 is a circuit diagram of an embodiment of the sense amplifier input voltage control circuit of the present invention, and FIG. FIG. 7 is a diagram showing sense voltage characteristics of memory cells of a matrix memory in a sense amplifier input voltage control circuit, and is a circuit diagram showing another embodiment of the sense amplifier input voltage control circuit of the present invention.

1...Memory matrix, 2...
-Sense amplifier circuit, 3...Input voltage control circuit, Q,,Q,2~Q,.

Claims (1)

[Claims] 1 A memory matrix circuit that combines load transistors, a sense amplifier circuit that controls and amplifies the signal from this memory matrix circuit, and a predetermined signal in the sense memory inserted between this memory matrix and the sense amplifier circuit. A memory cell is selected and the logic
0" information is read out and the potential at the connection point between the load transistor and the memory matrix circuit exceeds the sense level, it turns on, and the memory cell reads logic "1" information and the potential at the connection point drops below the sense potential. Then, the first transistor is turned off, the second transistor is controlled by the first transistor, and is turned on when the potential at the node is above the sense level, and is turned off when it falls below the sense level. 2
When the potential at the connection point exceeds the sense level, feedback is applied to lower the potential to a predetermined potential, and when the potential at the connection point becomes below the sense level, feedback is applied to raise the potential to a predetermined potential. A sense amplifier input voltage control circuit comprising: a third transistor; and an input voltage control circuit having a third transistor.