JPS6048761B2 - How to select an output device - Google Patents

Description

[Detailed description of the invention] The present invention relates to a method for selecting an output device.

2. Description of the Related Art Conventionally, for example, in factories producing various products, the operating times of automatic machines and the like have been controlled using pin ports.

According to this, a pin board was provided for each system of automatic machines, so even when a series of automatic machines were to be operated at the same time, the operating time had to be set for each system, which was cumbersome. Therefore, the present invention eliminates the drawbacks of the conventional method by generating operational outputs from gate circuits corresponding to each of a series of output devices by inputting two systems of commands to select the series of output devices. .

An embodiment of the present invention will be described below based on the drawings.

In FIG. 1, numeral 1 is a clock device, and numeral 2 is a data setting device composed of a microcomputer, etc., which sets 11 types of events as shown below using numeric keys. 23456 As described above, the time data from the ■ digit of the hour to the first digit of the second is set for the first to sixth events, and the model selection data is set for the seventh event.

In this example, this is data that instructs which system model is to be selected from among a plurality of models arranged for each system. Then, in the eighth and ninth events, channel selection data indicating which channel of the device of the model specified above is to be specified is set. Each of these devices constitutes an output device. The following events are specified individually and consecutively. Continuous designation means, when multiple devices are installed, selecting mutually adjacent devices at the same time to operate or deactivate them. In addition, single designation means designation to select a single device from among the plurality of devices and cause it to operate or deactivate. Finally, the control mode of the device is set for the eleventh event. That is, it instructs whether to operate or deactivate the device specified by the channel selection data. The devices to be controlled in this example include those that continue to operate by supplying short-time signal pulses, and those that operate only while the signal continues to be supplied. are different from each other, the former specifies operation, and the latter specifies operation maintenance.Also, when making the device inoperable, it specifies non-operation.3 is the main part of the present invention. The data detecting device generates a selection signal for each crosspiece and its control signal based on data sequentially read out from the data setting device 2.

4a...4c are output generating devices provided in each model, respectively. Each device is composed of a memory circuit, a transistor, a relay, etc., and stores the signal from the data detection device 3, and controls each device based on its output.

Next, let's talk about the specific configuration of the data detection device 3! second
This will be explained based on the diagram.

In the same figure, 5...11 is a latch circuit, and the respective input terminals P,......P,
(The read data is supplied in binary w-adic code in the order shown in the table above from the data setting device 2 in FIG. 1. Also, the terminal P... ＝, has
Terminal P,...P. Later species selection data...
......One pulse is supplied as the control mode data is supplied sequentially. 12...
・49 is a gate circuit, gate circuit 38...
・43 are Chiyang Miner 1 and 2 respectively...
. . generates selection signals for the devices shown in FIG.
The signal is supplied to the storage circuit 4c.

The input terminal Pl4 of the gate circuit 15 is supplied with one pulse from the data setting device 2 after the pulse is supplied to the terminal P9, and the output thereof causes the gate circuits 38...
・・・・・・The output of 43 is output from the output generator 4a...
. . . It is stored in the storage circuit 4c. 50
・・・・・・・・・56 are latch circuits 5...
It is a decoder that converts the output of . . . 11 into a downstream output, and the output terminals a . . . . 0...
...It generates 9 river force.

The decoder 50 is the output generator 4a of FIG.
...4c, and the decoder 56 generates a control signal to output the output generator 4a...4c.
c specifies the control mode of the device. 57...
...63 is an inverter, and inverter 58...
...63 constitutes a buffer circuit, and gate circuit 38
The input from . . . 43 is the command input for one system, and the input from the gate circuits 32 . . . 37 is the command input for the other system.

Next, the operation will be explained.

The data setting device 2 sequentially compares the set time of the device of each channel with the time signal from the clock device 1, and sequentially reads out the data of the matching channels, and terminals P,
・・・・・・・・・P. supplied to The following description will be made assuming that the read data is individually specified.
Terminal P,...P. The data supplied to the latch circuits 5 to 11 are commonly supplied to the latch circuits 5 to 11. First, time data is supplied, but at this time, no latch signal is supplied to the latch circuits 5...11 and the data is not latched. Next, when model selection data is supplied, a pulse is accordingly supplied to terminal P5, and the model selection data is latched into latch circuit 5. The output of the latch circuit 5 is converted into a downstream output by the decoder 50, and the output is used by the output generator 4a of FIG.
. . . One of 4c is selected. Next, the m-th digit of the channel selection data is terminal P1...
...P. , a pulse is supplied to terminal P6. At this time, the terminal 55b of the decoder 55 has a logical value '“
The output of the inverter 57 is held at the logical value "1". Therefore, gate circuit 1
2 and 13 are open, and the pulse supplied to the terminal P6 is supplied to the latch circuit 8, and is also supplied to the latch circuit 6 through the gate circuit 12. As a result, the second digit of the channel selection data is changed to the latch circuit 6,
It is latched to 8. Next, terminal P,...
P. When the one-digit digit of channel selection data is supplied to terminal P7, a pulse ι is also supplied to terminal P7. This pulse is supplied to the latch circuit 9, further passes through the gate circuit 13, and is also supplied to the latch circuit 7.

Therefore, the first digit of the channel selection data is latched into the latch circuits 7 and 9. . Next, single and continuous designation data are supplied, but single designation is currently being performed, and in this example, it is assumed that (10000) is set as this data. Therefore, terminal P,...
P. A pulse is supplied to the terminal P8 when all the signals are ``o''. As a result, the contents of the latch circuit 10 are all
The output of the decoder 55 is also held at ``0''.
'', and the output of the inverter 57 becomes ``1''.
is maintained. On the other hand, the output of the gate circuit 14 is ``0''
is held in the gate circuit 44...49
All outputs are kept at '1'. held. Finally, when the control mode data is supplied, the terminal P. A pulse is supplied to and latched by the latch circuit 11. In this example, it is assumed that (0000), (0001), and (0010) are set when the control mode is operation specification, operation hold specification, and non-operation specification, respectively, and this operation is for operation specification. shall be. Therefore, the terminal 56a of the decoder 56 is
It is held at ``1''. Once the data is latched as described above, a pulse is then supplied to the terminal PIO.

This pulse causes the gate circuit 24...
31 is opened, and the channel selection data stored in the latch circuits 6 and 7 is supplied to the decoders 51 and 52. For example, if this data is (0010), that is, if you specify the selection of the device on channel 2, then 1
Terminal a of the 0th place decoder 51 and terminal c of the 1st place decoder 52 become ``1'', and the output of the gate circuit 39 becomes ''
Inverted to 0''. Incidentally, the latch circuits 8 and 9 also store the same data as the latch circuits 6 and 7, but the gate 16 and 7
......23 are all held at '0', so the outputs of latch circuits 8 and 9 are output to decoder 5.
3,54 is not supplied. Therefore, the decoders 53 and 54
All outputs are 'o', gate circuit 32...
All the outputs of ...37 are held at '1', and the single power of gate circuits 44...49 is held at '1'. As mentioned earlier, when the output of the gate circuit 39 is inverted to ``0'',
The terminal 39a is inverted to ``0'', and a selection signal for the channel 2 device is generated.

On the other hand, the level of the output terminal 15a of the gate circuit 15 is inverted by the pulses supplied to the terminals P and O, thereby causing the selection signal from the terminal 39a and the decoder 5
The operation designation signal from the terminal 56a of channel 6 is read into the memory circuit of the output generator 4a...4c selected by the decoder 50 in FIG. works. The other channel devices are also controlled in the same manner as described above. Next, the operation when consecutive designations are made will be explained.

For example, assume that devices from channel 1 to channel 5 perform similar control at the same time. In this case, as continuous specified data for the device on channel 1 (0001)
It is assumed that (0010) is set as continuous specification data for the device of channel 5. Note that no settings are made for data from channel 2 to channel 4. Then, when the data of channel 1 is read out sequentially at the set time, the model selection data is sent to the latch circuit 5, and the channel selection data is sent to the latch circuit 6...9, as described above. That is, the latch circuit f6,
(0000) is latched in circuit 8, and (0001) is latched in circuits 7 and 9.

Next, the continuous designation data (0001) is latched by the latch circuit 10, and the terminal 55b of the decoder 55 is inverted to ``1''. Finally, the control mode data is latched into the latch circuit 11. When a pulse is supplied to the terminals P and O at 5, the gate circuits 24...31 are opened and the outputs of the latch circuits 6 and 7 are sent to the decoder 5 as in the previous explanation.
1,52. Therefore, the output of the gate circuit 38 is inverted to ``o'', and the output of the inverter 58 is ``o''.
Invert to 1''. Now, the terminal 55b of the decoder 55 outputs the output of the gate circuit 14, that is, the gate circuit 44.
......Since the single power of 49 is kept at ``1'', the above level reversal of the inverter 58 causes
The outputs of the gate circuits 44...49 are sequentially output.
Reverse to ゛o''. However, since the gate circuit 15 is closed by the output of the inverter 57, the above-mentioned pulses to the terminals P and O do not pass through the gate circuit 15 and are sent to the terminal 38a.
. . . The output from 43a is not stored in the storage circuit of the output generator. In this state, data on channel 5 is next read out.

First, since the model selection data is the same as channel 1,
The contents of the latch circuit 5 remain unchanged. Next, channel selection data (0101) is supplied to the inverter 57.
Since the gate circuits 12 and 13 are closed by the output of the gate, no latch signal is supplied to the latch circuits 6 and 7.
The contents of each are held in (0000) and (0001). On the other hand, latch circuits 8 and 9 each have (000
0) and (0101) are latched. Next, continuous designation data (0010) is supplied and latched by the latch circuit 10, and the terminals 55b and 55c of the decoder 55 are
40,,441,,. Finally channel 1
The same control mode data is supplied, and the contents of the latch circuit 11 remain unchanged.

- Now, due to the level inversion of the terminal 55c of the decoder 55, the gate circuit 16...23 is opened, and the contents (0000) and (0101) of the latch circuits 8 and 9 are supplied to the decoders 53 and 54. , the output of the gate circuit 36 is '
Inverted to '0'. Therefore, the one input of the gate circuit 48 is inverted to ``0'', its output is inverted to ``1'', and the output is inverted to ``1'', and the output is inverted to ``1'', and the output is inverted to ``1'', and the output is inverted to ``1'', and the output is inverted to ``1'', and the output is inverted to ``1'', and the output is inverted to ``1'', and the output is inverted to ``1'', and the output is inverted to ``1'', and the output is inverted to ``1'', and the output is inverted to ``1'', and the output is inverted to ``1'', and the output is inverted to ``1'', and the output is inverted to ``1'', and the output is inverted to ``1'', and the output is inverted to ``1'', and the output is inverted to ``1''. Invert to 1''. Therefore, terminal 3
8a......Up to 42a are held at ``0''. On the other hand, the above level S of the terminal 55b of the decoder 55
Due to the inversion, the output of the inverter 57 is inverted to ``1'', so when a pulse is supplied to the terminal PIO, it passes through the gate circuit 15. Therefore, the terminal 38a...
The selection signals for the devices of channels 1 to 5 from 42a and the control signal from the decoder 56 are output from the decoder 50 of the output generators 4a...4c in FIG. The selected one is stored in the memory circuit, and the equipment of channels 1 to 5 is controlled by its output. As described above, when controlling devices on multiple consecutive channels in the same way at the same time, you only need to set the data for the first and last channels.
This simplifies the data setting operation.

In the above embodiment, the control mode is set to three types: operation, operation J maintenance, and non-operation, but for example, the device may be controlled in only one type, that is, only operation, only operation maintenance, or only non-operation.

In this case, there is no need to set control mode data, and the latch circuit 11 and decoder 56 are also unnecessary, and the output of the gate circuit 44...49 allows one type of device to be set. All you have to do is control it. As detailed above, according to the present invention, different command inputs are supplied to the gate circuits respectively corresponding to the first and last of a series of output devices among a plurality of output devices. Since the operating output is generated from the corresponding gate circuit, multiple output devices can be selected by inputting commands from two systems, and the data for selecting each output device can be programmed in advance and selected automatically. When used for this purpose, it is only necessary to set data for the first and last output devices to be selected, simplifying the data setting operation. Therefore, the storage capacity of the device for programming data can also be small.

[Brief explanation of drawings]

FIG. 1 is a block diagram schematically showing an embodiment of the present invention;
FIG. 2 is an electrical circuit diagram showing details of the main parts of FIG. 1. 44-49...Gate circuit, 58-63...
...buffer circuit.

Claims (1)

[Claims] 1 Multiple stages of gate circuits are provided so that the output of the previous stage gate circuit is input to the next stage gate circuit via a buffer circuit, and a selection input is commonly supplied to the other inputs of each gate circuit, and the above One system of command input is supplied to the input side of the buffer circuit, another system of command input is supplied to the output side of the buffer circuit, and one of the above two systems is supplied to the first stage gate circuit among the gate circuits to be selected. Supply operation commands from one system of command input to put the first stage gate circuit into operation state,
The operating output from the first stage gate circuit is sequentially transmitted to the subsequent stage gate circuit to bring the latter stage into operation, and among the gate circuits to be selected, the operation output is transmitted to the next stage gate circuit following the final stage gate circuit. A non-operating command is supplied from the command input of the other system among the two systems to put the gate circuit in the next stage in a non-operating state, and the non-operating output from the gate circuit in the next stage is sequentially transmitted to the gate circuit in the subsequent stage following the next stage. A method for selecting an output device, in which the output device is selected by transmitting the signal to the gate circuit, rendering the gate circuits in the subsequent stages inactive, and causing the gate circuit to be selected to generate an operational output.