JPS6048619A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To attain high accuracy of an analog output by applying an error optimizing operation to a digital-analog converter at a proper time before or during the use. CONSTITUTION:A multiplexer 15 is provided to an input side of a code converting section 12, the multiplexer 15 is controlled from a control section 16 through a terminal 19 so as to select the A side input while the content of the code converting section 12 is written, one of current sources 21-2k is selected one by one, is current value is recognized and an error corresponding thereto is obtained. An input/output relation of the code converting section 12 is selected so as to optimize the error rate based on the error. When the error optimizing mode is started, the content of the code converting section 12 is rewritten by the control section 16 and the optimizing processing is conducted, then the conversion with high accuracy with decreased error is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a conversion device for converting a digital signal into an analog signal, which is suitable for cases where the number of input bits is large.

<Prior art> In a conventional digital-to-analog converter, when the number of digits of the input digital signal is large, even a slight error in the current value of the current source for the upper digits of the input digital signal has a large influence. I can do it. Therefore, for multiple bits of the upper digits of the digital signal to be input, 10
Convert it to a decimal number, set up multiple current sources with the same current value as many as the maximum number, select the current sources as many times as the converted decimal number, output the current, and convert these currents. was added to produce an analog output of the digital signal of the upper digit.

By converting the upper digits in this way, error reduction is advantageous in achieving high-precision technical analog conversion.
In addition, the amplitude of spike-like noise, so-called glitch, that occurs when switching input digital signals can be reduced. However, the current values of the multiple current sources corresponding to the upper digits each have a slight error, and these errors are mutually influenced and the digital input value of the upper digit is
For certain input values, the error becomes extremely large.
There was a drawback that the error rate decreased significantly for a specific input value, that is, the error rate was not uniform.

FIG. 1 shows an example of the configuration of a conventional high-precision digital-to-analog converter. Digital signal input terminals 11 to 1r+.

Digital signals B+-Bn to lH++-In+m, respectively.
.

Bn+ t-Bn++n is input, and each of these digital signals B1 to Bn, Bn+1 to Bn+m is sequentially lowered by 1/2 from the analog voltage outputted to the analog output terminal 11 by the signal B+ until it reaches the signal Bn+m. It is weighted in binary so that it becomes a value.

Top signal B I (MS B: Mo5t 51g
n1f 1cant Bit) to the signal Bn are input to the code conversion unit 12 and converted from binary weighting to a signal having a decimal weighting range. Therefore, now the signals B1-B
If the code conversion unit 12 converts the 4 bits of 4, the conversion output is converted so that 15 equal weights are output to one or more of the 44 terminals. The current switches 31 to 3k are controlled by each output (k=2-1.) to the code converter 120, and the current switches 3H+
1-3n+m is a digital signal B n + 1 to B n
+m respectively. A current weighted with the same value is output to the current sources 21 to 2, and the current sources 2n+1 to
2B+m is binary weighted to decrease by 1/2 and outputs a current. 2g−+ for these current sources 21 to 2;
-+~2n+m each current I+~Ik+In+
1 to In+m to the corresponding current switches 31 to 3, 3
According to the control state of n++ to 3n+m, the signals are supplied to the adder circuit 13, added, and output to the output terminal 11. 'A constant voltage for operating the current sources 21 to 2k and 21+1 to b is supplied from a constant voltage source 14.

Therefore, when the upper 4 bits are converted into a decimal number by the code converter 12 and the lower 14 bits are used to control the corresponding current switch using a binary number, that is, = 15, n = 4, m = l 4
In the case of , each pitch of the input digital signal) B+ to B+
The relationship between s and the current sources 21 to 229 is as shown in FIG. Upper bits B1 to B4 are current sources 21 to 21
s, and in that case, the number of current sources selected is equal to the output of the binary upper bit converter 12, that is, the number of numerical values converted to a decimal number. As shown in FIG. 3, when only bit B4 of the upper bits B1 to 134 is input, this is the smallest value, and only switch 315 is turned on so that only current source 215 is output. When only bit Ba is input, its decimal number is 2, switch 314.3+5 is turned on, and current source 214,
A current is output from 215. Bit f3g.

When B4 is input together, the decimal number thereof is 3, switches 81g to SI5 are turned on, and the outputs of current sources 218 to 215 are output together. Similarly, the number of currents corresponding to the converted decimal number is output. However, for the lower bits B5 to Bus, the current source 216
229 correspond to one each, and only the current of the current source corresponding to the input bit is output.

By doing this, the current value of the current source corresponding to the upper bit does not have to be so large, and therefore the accuracy of the current value can be made relatively high, allowing high-precision digital-to-analog conversion. This is easier to accomplish and can reduce the amplitude of spike-like noise that occurs when manually input digital signal values are input.

However, in this conventional digital-to-analog conversion device, the code conversion section 12 is composed of wired logic, and when it was first designed, the positional relationship of the output terminals that output corresponding to the upper digital input bits was fixed. . Regarding the current values 1r to Ik of the current sources 21 to 2, it is relatively easier to reduce each error than when binary weighting is applied, and the error can be made smaller. The source current value includes some errors.

For these reasons, the output error rate becomes significantly large depending on the input digital signal, and the error rate becomes small for other input digital signals, so that the error rate may not be uniform.

That is, for example, as shown in FIG. 4, it is assumed that the error rate for the current values of current sources 21 to 28 is +α, and the error rate of each current value for current sources 29 to 2+s is -α. In this case, the error rate of the conversion output for the digital input of upper bits B+ to B4 is O when BIIB21BIIIB4 is 1110, as shown in Figure 4, and when B ]B 2 B 8B 4 is 0111, the error rate is 7α, which had the disadvantage that the error rate varied greatly. In particular, in this example, only the maximum pitch Bx is 1, that is, input digital values around 1000 have a large error rate, and input digital values range from 10'OO to 0.
The closer it gets to 001 and the closer it gets to 1111, the more the error rate decreases.

<Summary of the Invention> The purpose of this invention is to convert an input digital signal into a decimal number, and output an analog signal corresponding to the input digital signal by controlling the output of a current source whose weight is determined by the converted output. In a digital-to-analog converter, regardless of the value of the input digital signal, the output analog 4
The error rate of No. 8 is equalized, and the error rate is adjusted so that it becomes the optimal error rate as a whole. f...! The purpose is to obtain an analog output with a high degree of 7FA.

In this invention, an input digital signal is converted into a decimal number by a code converter, and the number of outputs corresponding to the input digital signal is outputted, and current switches for current sources of the same weight are controlled by these outputs. The output of the adder circuit which outputs the current and deviates from it is converted into a digital signal by an AD converter.On the other hand, switch selection means is provided to select and control the current switches one by one regardless of the input digital signal, and each of the current switches is 'Turn on the current switches one by one
Control the HII, convert the currents of the valley current source and the bottom current into digital signals using the above A and D converters, and compare the digital signals with a predetermined standard current value to determine the error. and stored in the error storage means. Based on the stored errors of each current source, the input digital signal and the code converter to be output from the input digital signal are The relationship with the output terminal is selected by the error optimization means. The input/output relationship of the code converter is changed based on the result selected by the error optimization means.

In other words, the relationship is changed so that the current source is selected corresponding to the valley input digital signal so that the error rate is almost the same for all input digital signals. By performing the error optimization operation before using the digital-analog converter or at an appropriate time while the digital-analog converter is in use, the error rate becomes uniform and highly accurate conversion can be performed. .

<Embodiment> FIG. 5 shows an embodiment of the digital-to-analog converter according to the present invention, in which the same reference numerals are used for γ14 corresponding to FIG. 1. In the present invention, a code converter 12 is used whose input/output relationship can be freely changed. For example, a memory capable of reading and writing is provided as the code converter 12, and addresses A1 to A are stored in this memory.
When n is input, it is internally decoded and the number of addresses from 1 to 1 is selected, and each address consists of bits from b+ to bk as shown in Figure 6, that is, one word river (
It is a bit memory, and when one of these addresses is read, the contents of the bit are outputted as 81 to Sk. These are given as control signals to the current switches 31 to 3k.

It is possible to select only one of the current sources 21 to 2 and supply that current to the output terminal 11. Therefore, in this embodiment, a multiplexer 15 is provided on the input side of the code converter 12, and the multiplexer 1
5 is the terminal of the control circuit 16] B
+ to Bn and send address A1 to code converter 12.
Alternatively, data C+ to Cn can be input from the control unit 16 and the address A1 can be given as address A1.
3 to be supplied to the code converter 12 as An to An, and further provide a read/write control signal to the code converter 12 from a terminal 17 of the controller 16 to the code converter 12,
Also, by applying write data D+ to 1)k from the terminal 18, Dl to Dk can be respectively written to each bit (memory cell) bl to bk at a position specified by addresses A1 to An. .

This writing is performed for each current source as described above.

Therefore, when the upper bits are 4 bits B1 to B4 as in the above example, as shown in FIG. For the 155-strip land, the number 1 has a ring) Only b+s is 1, and the 2-strip area has a ring l-b
Each address is stored so that only one different bit is set to 1, such that only +4 is set to 1. In other words, the brake 1 section 16 specifies each of these addresses and writes the corresponding data D+ to Dk by giving them to the code converting section 12 from the terminal 18.

In this way, when the contents of the code conversion section 12 are in a mixed state, the control section 16 controls the multiplexer 15 through the terminal 19 so as to select the A inputs.
The address data C] to Cn specified by 6 are given to the code converter 12, whereby one address is extracted and one of the current sources 21 to 2 corresponding to the address is selected and output. Become.

The output analog signal obtained at the terminal "1" is converted into a digital signal by the AD converter 21, and the fm value thereof is taken into the control section 16.

In this way, each current source is selected, its current value is known, an error is calculated, and the input/output relationship of the code converter is selected based on the error so that the error rate is optimized. Therefore, when this error optimization mode is started as shown in FIG. 8, the code converter 1
2, its contents are rewritten by the control unit 16 as shown in FIG. In step S2, the contents of the address designation memory 22 in the control section 16 are read out and the data C
Apply I to Cn as an address to the code converter 12 through the multiplexer 15, and for example, in FIG. This current Il is output to the output terminal 11 through the adder circuit 13.
s is taken into the control unit 16 by the AD converter 21 (step Sg). The error of this fetched value with respect to a predetermined value is calculated, and the error is stored in the error memory 23 in correspondence with the current source 21s in step S4. Next, in step S5, the content i of the addressing memory 22 is incremented by 1, and in step S5
In step 6, determine whether the new content i matches k,
If they do not match, the process returns to step S2 and the data C]~Cn indicating the new content 1 of the addressing memory 22 is
is output and given to the code converter 12. Repeat the same process below. When l matches k in step S6, this current error detection process R1 ends and the optimum process llj
Moving on to chemical R2.

In the error optimization process R2, for example, in step S7, a current source with a minimum error with respect to the highest pitch I-MSB of the digital input is selected. In other words, 8 of the current sources 21 to 215 are selected for the top 4 bits shown above) B+ to [data with MSB=1 as shown in FIG. 3 out of 34 data]000. However, from the errors of each current source stored in the error memory 23 measured in the current error detection process R+, the one with the smallest absolute value is selected in order, and the sum of these eight errors is the polarity. The minimum combination is selected by considering the following.

For example, as shown in FIG. 9, "current sources 21.28.25.
Assume that 27, 29, 211, 218, and 215 are selected. Next, in step s8, one is subtracted from these selected items, and an operation is performed such that the overall error rate is minimized when the subtraction is made. In step s9, the counter 24 in the control section 16 is incremented by a-1. This a Id k −
It is the value obtained by dividing 1 by 2, and this new minus 1 content a of the counter 24 is the step S+.

It is determined whether or not the current source is 0. If it is not 0, the process returns to step s8 and one of the previously selected current sources is removed again to perform an operation such that the error rate at that time is minimized. Do the same below. When a is determined to be 0 in step sto, the process moves to step S, and in step S7, one of the remaining current sources is added to the selected current source so that the error rate at that time is minimized. Next, in step S12, the counter 24 is incremented by a+1. The initial value of this a is flat-1
Next morning, it is checked in step SI8 whether the contents of the counter 24, which have been incremented by a+1, match k or not. If they do not match, the process returns to step SL+, and as before, the remaining current sources are Add one so that the overall error rate at that time is minimized. Similarly, when a becomes k in step S]g, the optimization process R2 ends and the process moves to step S14.

In step S14, for 100o, each selected current source corresponds to a value one smaller than 1000, and each selected current source 1ooo corresponds to a selected current source for a value sequentially larger than 1000. The contents of the code converter 12 are rewritten so that the related person's output can be obtained from the code converter 12. The stored contents of the code converter 12 are in a state as shown in FIG. 9, for example.

After rewriting the contents of the code conversion unit 12 in this way, the control unit 16 controls the multiplexer 15 to select the B input terminal, that is, the input terminals 11 to ln side, so that the digital inputs to the input terminals 11 to In+m are respectively By inputting the signal and selecting the switches 31 to 3n+m as in the conventional case, analog conversion to the digital input is performed. In this case, the code conversion unit 12 is controlled so that the conversion of the upper bits has an optimum error as described above, so that the conversion accuracy is high.

As shown in FIG. 9 with the same reference numerals attached to parts corresponding to those in FIG.
is provided to select one of the output of the code conversion section 12 and the data of the output terminal -17 of the control section 12,
Alternatively, the voltage may be applied to 3k to 3k. When doing this, there is no need to rewrite the contents of the code converter 12 as shown in FIG. Therefore, the time required for input/output related recombination processing by the code converter 12 is shortened. However, when converting the digital inputs of the input terminals II to 1n+m into analog signals, more multiplexers 25 are inserted on the upper bit side, so the time required to obtain the converted output becomes longer.

As described above, according to the digital-to-analog converter according to the present invention, the error rate is high enough to obtain the correspondence between the input and output of the code conversion section that generates outputs at the number of output terminals corresponding to the numerical value of the input digital signal. It is possible to carry out the conversion process in an optimal manner, and therefore to obtain highly accurate data with few errors. As the code converter 12, RA
ROM may be used instead of M.

[Brief explanation of drawings]

Figure 1 is a block diagram showing a conventional digital-to-analog converter, Figure 2 is a diagram showing the correspondence between this input digital signal and current sources, and Figure 3 is a diagram showing the relationship between the conventional upper bits and the current sources to be selected. 4 is a diagram showing an example of the relationship between the error rate of each current source and the error rate for various digital inputs. FIG. 5 is a block diagram showing an example of a digital-to-analog converter according to the present invention. FIG. 6 is a diagram showing an example of the contents of the code converter, FIG. 7 is a diagram showing the memory contents of the code converter in error detection processing, and FIG. 8 is a flowchart showing an example of the processing procedure in error rate optimization control. , FIG. 9 is a diagram showing an example of the storage contents of the code conversion unit in the obtained optimization, and FIG. 10 is a block diagram showing another example of the digital-to-analog conversion device according to the present invention. II to In+m: Input terminal, 2I to 2n+m: Current source, 31 to "n+m: Current switch, 11: Output terminal, 12: Code converter, 14: Constant voltage circuit, 15+
25: multiplexer, 16: control unit, 2 ], :
AD converter, 23: error storage memory. Agent Takuji Kusano 7 figure body 9 figure O 8 decoy

Claims (1)

[Claims] (1) A code converter that receives an input digital signal and generates output from predetermined output terminals in a number corresponding to the digital value of the human input signal, and a code converter that is provided in a number equal to the number of output terminals of the code converter. a plurality of current sources that generate currents of the same magnitude, and a plurality of current switches that are provided on the output sides of the current sources and that are controlled by the output of the corresponding output terminals of the code converter. and an adder circuit that is supplied with the outputs of these current switches and adds the currents to output an analog signal corresponding to the input digital signal, and detects the error in the current value of each current source from the output analog signal of the adder circuit. an error detection means; an error storage means for storing errors of each detected current source; and an error storage means for storing an error of each detected current source; an error optimization means for selecting the relationship between the digital signal and the output terminal of the code conversion section to be output; and an input/output of the code conversion section so as to match the optimization result obtained by the error optimization means. A digital-to-analog conversion device comprising means for changing a relationship.