JPS6048611A - Test circuit of multiplex switched capacitor filter - Google Patents

Abstract

PURPOSE:To measure each channel characteristic of a multiplex filter even with one test output terminal by constituting the test circuit with an output selecting circuit and a switch group, connecting all other terminals of the switch group and using the connected terminal as an output terminal. CONSTITUTION:Other terminals of switches S101-S104 are connected in common and the common terminal is connected to the test terminal T0. Further, an output of an output selection circuit SE comprising input terminals T1, T2, inverters IN1-IN6 and 3-input NOR gates No.1-No.4 is connected to a control terminal of the switches S101-S104. When the level of the input terminals T1, T2 is brought into a low level L respectively, a phi1 waveform is outputted to the output of the 3-input NOR No.1 (No.2-No.4 outputs are all at L level) and the swtich S101 of a switch group SWG is switched in synchronizing with the phi1. When a signal is applied to the input IN, an output of a channel 1 in synchronizing with the clock phi1 appears at the test terminal T0 so as to attain the characteristic test of the channel 1.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical field to which the invention pertains The present invention relates to a time-division multiplex switch and a fixed capacitor filter, and more particularly to a test circuit for fully testing the characteristics of each multiplexed channel.

(2) Description of the Prior Art In testing this type of filter, since the output signals are multiplexed, it is necessary to take the timing and synchronization cost for multiplexing. Therefore, a method can be considered in which all the switches of the number multiplexed to the output of the filter are arranged and operated at each timing, and the outputs of the valleys are measured.

However, as the number of multiplexing stages increases, the number of output terminals also increases.
If this happens, the area of cha 1 will increase.

(3) Purpose of the Invention The present invention is an output selection circuit, and by selecting a switch that operates in synchronization with the clock of a multiplexed switched capacitor filter, all the multiple specific capacitance outputs can be selected with one output terminal. It provides a complete multiplexed switch and Chido Yayabashita filter test circuit to enable testing.

(4) Configuration of the Invention The uninvented test circuit includes a time division multiplexed switched capacitor filter, an output selection circuit that selects all outputs in synchronization with the time division clock of the multiplexed switched capacitor filter, and the multiplexed switched capacitor filter. It consists of a group of switches that are connected to the output of the capacitor filter and operate as a switch for the output of the output selection circuit, and by connecting all the other terminals of the switch group, the number of test output terminals is reduced to one. This is a multiplexed switched capacitor filter test circuit that can measure the characteristics of each channel of a multiplexed filter.

(5) Embodiment Next, the case of a 4-multiplex system according to the present invention will be explained with reference to the drawings.

FIG. 1 is a configuration diagram in the case where each multiplexed channel has a test terminal. Operational amplifier A capacitor Cl-05
and a time division multiplex switch composed of switches S1 to 812, and a switch group S composed of switches 8101 to 5104 to the output of the chidock apascitor filter MP.
One terminal of WG is connected, and switches 5ioi to 81
Each of the other terminals of 04 is connected to a test terminal T.
Ox-To,i is connected.

When the input INK signal is applied here, each switch operates at the timing shown in Figure 3, so regarding the test terminal TUI, φ
, when ON, the output of channel l appears on TO1 and φ, O
When it is FF, no other channel output appears, so only channel 1 is tested. Similarly test terminal 'r
Channel 2 on 02. Channel 3 on TO3,
TO4 allows you to test the characteristics of channel 4. However, since there are as many as four test terminals, this increases the chip area, which poses a problem when integrated into an IC.

Next, a detailed embodiment of the present invention will be explained with reference to FIG. 2. The main parts in FIG. 2 are the same as in FIG. 1, but the other terminals of the switches 8101 to 5104 are connected in common and connected to the test terminal TO. In addition, input terminals TI and T2
, Inverter INI ~ IN6 ,! = 3 man power N
The output of the output selection circuit 8E composed of the O-gates NOI to NU4 is switched.

It is connected to the control terminals of channels 8101 to 5104.

Input terminals TI and T2i are each low level (hereinafter “L”)
), the φ1 waveform is output as the output of the three-manpower N0RNOI, and the NO2, NO3, and NO4 outputs are all "L") The x inch 5lo1 of the switch group 8WG switches in synchronization with the φ violet. Here, when a signal is applied to input IN, a black signal is output to test terminal To.

The output of channel 1 synchronized with φri appears, making it possible to test the characteristics of channel 1.

Similarly, T1 is at high level (hereinafter referred to as ``'H'').

Tz "In the case of LJ, only switch 5102 is closed and φ
Characteristic 2 of channel 2 in synchronization with 1, TirLJ, T2
[In the case of HJ, only switch 8103 uses clock φ3
In synchronization with φ4, the characteristics of channel 3 can be tested at T1, and in the case of T2[J, only the switch 5104 is closed.

(6) Effects of the Invention As explained above, the present invention makes it possible to measure each channel characteristic of a multiplexed switched capacitor filter with one test output. In addition, when the output is reduced to one IC, a measuring circuit which is very advantageous in terms of the number of bins and chip area can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a circuit diagram of an example in which a test terminal is provided for each multiplexed channel, FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is a diagram showing the timing of a multiplexing clock. In the diagram, IN......input terminal, OUT
...Output terminal, T(J, TOI-TO4...
...Test terminal, A...Operation amplifier, C1-c5
... Capacitor, MP ... ° Multiplexed switched capacitor filter, SWG ... Switch group, SE ... Output selection circuit L Tl. T2...Selection input terminal, INI~IN6...
...Inverter, NO1~No4-=・3 person NOR, gate, s1~s12°8101~5104・
...It's a switch.

Claims (1)

[Claims] a time-division multiplexed switched-capacitor filter; an output selection circuit that selects an output in synchronization with a time-division clock of the multiplexed switched-capacitor filter; 1. A multiplexed switch/tidal capacitor filter test circuit comprising a group of switches that are operated by the output of a selection circuit, and wherein the other terminals of the switch group are all connected to serve as output terminals.