JPS6047766B2 - crystal oscillation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a crystal oscillation circuit, which suppresses unnecessary radiation by reducing the oscillation output amplitude and facilitates integration into an integrated circuit (IC).

Since crystal oscillation circuits have superior frequency stability compared to other oscillation circuits, they have recently come to be used in a large number of various digital devices.

FIG. 1 shows a conventional crystal oscillation circuit. 1 is a phase inversion amplifier to which a self-biasing resistor 2 is connected; 3
is a crystal oscillator, and 4, 5, and 6 are resistors and capacitors for frequency fine adjustment, respectively.

Here, for example, a commercially available C-M
If an OS logic IC is used, its oscillation output amplitude will reach the applied power supply voltage. When the oscillation output amplitude increases in this way, unnecessary radiation becomes a problem. Furthermore, in devices such as PLL (phase-locked loop) synthesizer receivers in which digital circuits and analog circuits coexist, interference with other signals cannot be ignored. The latter becomes a problem especially when the use of ICs progresses. In order to eliminate this drawback, a crystal oscillation circuit as shown in FIG. 2 can be considered.

That is, the crystal oscillation output is clamped by a clamp circuit composed of two silicon diodes 8 and 9 connected in parallel in opposite directions and a potential generation circuit. With this configuration, the oscillation output can be suppressed to an amplitude of 1.4V, which is twice the forward threshold voltage O of the silicon diode, 7V, without changing the operating point of the phase inversion amplifier 1.
It is possible to prevent large signals that would cause unnecessary radiation from being output to the external terminals of the IC. In the circuit shown in FIG. 2, a phase inverting amplifier 10 is used as a potential generating circuit, and its input and output terminals are connected directly or through a resistive load to obtain a DC voltage. , the circuit shown in FIG. 2 can be easily integrated into an IC. Therefore two 7s
When the phase-inverting amplifiers 1 and 10 are formed on the same semiconductor substrate, it is possible to make the temperature conditions and element parameters approximately equal, so that the DC operating voltage of the phase-inverting amplifier 1 and the voltage at node No. Since they can be made to match, the voltage at node N2 can be stably clamped after all. 7
is a phase inversion amplifier for amplifying the oscillation output to the amplitude required to drive the subsequent digital circuit, for example, and is formed by an IC and is set at the same operating point as amplifier 1. .

By the way, the circuit in Figure 2 has a very small oscillation output amplitude (node N2 in Figure 2) and oscillates stably without depending on the power supply voltage, but in order to reduce the oscillation output amplitude, had the disadvantage that the output impedance of the phase inversion amplifier 10 had to be made small. The present invention eliminates such drawbacks, and will be described in detail below with reference to an embodiment of the present invention shown in FIG. 3 and its operational waveform diagram (FIG. 4). In addition, in FIG. 3, the same components as in FIG. 2 are given the same figure numbers as in FIG. ing. When the voltage difference between the node N3 and the node N2 increases and reaches the threshold voltage of the diode (approximately 0.7 .mu. in the case of a silicon diode), the diode 9 is turned on and a period (t1) begins.

First, the voltage at node N1 becomes high, and the voltage at node N2, which is inverted and amplified, becomes low. The voltage at node N3 connected via diode 9 becomes low, and the voltage at node N4 also becomes low via resistor 11. Then node N
The voltage at node N3, which is inverted and amplified from the voltage at node N4, has a stronger effect of clamping the voltage at node N2 via diode 9. Further, the voltage at the node N is a value obtained by dividing the voltage at the node N2 and the voltage at the node N3 by the resistor 11 and the resistor 12, and the voltage at the node (Nl, N2, The voltages of N3 and N4) are balanced.
Therefore, if the resistor 11 is made smaller than the resistor 12, the change in the voltage at the node N2 will be transmitted as is to the node N4, so the voltage amplitude at the nodes Nl and N2 will be reduced.
Balance is achieved in a state where the voltage amplitudes of nodes N3 and N4 are increased. Now, when the voltage at node N1 decreases again and the voltage at node N2 increases, the voltage at node N4 increases.
The voltage will also increase.

In this way, the clamping effect of the voltage at node N3 on the voltage at node N2 weakens, and finally the voltage difference between nodes N2 and N3 becomes less than the threshold voltage of the diode, turning off diode 9 and transitioning to period (T.). do. During this period, both diodes 8 and 9 are in the off state, so
The clamping effect by the diode disappears, and the node N2
The voltage at nodes N3 and N4 suddenly increases, and the voltages at nodes N3 and N4 change through resistors 11 and 12 so as to be balanced.

In other words, the voltage at node N3 decreases rapidly. Furthermore, the fourth
In the figure, when the voltage at node N4 is constant, phase inverting amplifier 1
The reason why this is set higher than the DC operating voltage of 0 (which is approximately equal to the average voltage of node N4) is to simplify the explanation. For example, if it is assumed that the voltage at node N4 is lower than the above DC operating voltage at the beginning of the period, the voltage at node N3 will remain high and the voltage at node N2 will also rise rapidly, so node N
The voltage at node N3 also increases rapidly, and therefore the voltage at node N3 also decreases rapidly. In this way, node N2 and node N
When the voltage difference between 3 and 3 reaches the threshold voltage of the diode,
Diode 8 is turned on and clamping by diode 8 is now activated (period T3).

The operation during period T4 is similar to the operation during period T2. As an example, commercially available C-MOS (
Using National Semiconductor's 74C00),
IMHZ crystal oscillator as 3, 20 each as 5 and 6
0PF capacitor, 2 as 330KΩ resistor, 4
When a resistor of 1 KΩ is used as , silicon diodes are used as 8 and 9, and resistors of 3.3 KΩ are used as 11 and 12, the voltage at node N2 becomes 1.1 PP.

Further, when the resistance 11 was set to 1.5 KΩ under the same conditions, the resistance was 0.6 PP. In the circuit shown in FIG. 3, 11 and 12 have been described as resistors, but they may be made of resistive elements, such as FETs. According to the present invention described above, the oscillation output voltage regardless of whether the diode is on or off is always detected, and during the period when the diode is on, it is clamped with the phase-inverted output voltage, and during the period when the diode is off, the oscillation output voltage is clamped with the reverse polarity voltage in advance. (for example, by lowering the voltage at node N3 after a certain period), the period in which the diode is on is longer than in the circuit shown in FIG. It is not necessary to make the output impedance of the node N2 so small; if the value of the resistor 11 is made small, the voltage amplitude at the node N2 becomes small. Furthermore, when the two phase-inverting amplifiers 1 and 10 are formed on the same semiconductor substrate, the oscillation output voltage can be stably clamped by making the DC operating voltages of both substantially the same. In addition, when the circuit shown in FIG. 3 is integrated into an IC, the terminals are nodes N1 and N2, and it is possible to reduce the influence on analog circuits outside the IC, and the signal inside the IC is connected to the phase inversion amplifier 7. You can use the output of

[Brief Description of the Drawings] Fig. 1 is a conventional crystal oscillation circuit diagram, Fig. 2 is a crystal oscillation circuit diagram with a clamp circuit, Fig. 3 is a crystal oscillation circuit diagram according to the present invention, and Fig. 4 is its operation. There is a waveform diagram. 1, 10... Phase inversion amplifier, 3... Crystal resonator, 8, 9... Clamp diode.

Claims (1)

[Scope of Claims] 1. A crystal oscillator configured by connecting a crystal resonator between the input and output terminals of an amplifier, a phase inversion amplifier having a resistive load connected between the input and output terminals, and one end connected to the crystal oscillator. a clamp circuit having one end connected to the output end of the oscillator and the other end connected to the output end of the phase inversion amplifier; and a resistive load having one end connected to the output end of the crystal oscillator and the other end connected to the input end of the phase inversion amplifier. A crystal oscillation circuit consisting of 2. The crystal oscillator circuit according to claim 1, wherein the clamp circuit comprises diodes connected in parallel. 3. The crystal oscillation circuit according to claim 1 or 2, wherein the amplifier and the phase inversion amplifier are integrated on the same substrate, and their DC operating voltages are made substantially the same.