JPS6047627B2 - memory controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory controller that speeds up memory read times for two memory read sources sharing a storage unit.

In systems configured with two memory read sources and shared memory, memory reads from one memory read source typically take priority over memory reads from the other memory read source.

However, conventionally, even if a memory read request occurs from a high-priority memory read source while a low-priority memory read source is executing a memory access, it will not be processed until after the low-priority memory read source has finished reading. The request will be accepted. Therefore, the actual effect of priority is
This was the case only when memory read requests were generated from both memory read sources at approximately the same time. Therefore, even high priority memory read sources did not always provide the highest read speed, and the read time was not constant.
The present invention eliminates the above-mentioned drawbacks and allows high-priority memory read sources to read at the fastest read time inherent in shared storage units, while also allowing low-priority memory read sources to read at the fastest possible read time. An object of the present invention is to provide a memory control device that can be shortened in size.

A detailed explanation will be given below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a memory address register MARI, which is a register for setting a memory address on the memory read source 1 side. 2 is memory address register MA
R2 is a register for setting a memory address on the memory read source 2 side.

3 is a storage unit MEM.

4 is a D flip-flop F/F1, and when the value of this flip-flop is ``1'', it indicates that the memory unit MEM3 is being accessed from the memory read source 1.

5 is a D flip-flop F/F2, and when the value of this flip-flop is ``1'', it indicates that the memory unit MEM3 is being accessed from the memory read source 2.

Reference numeral 6 designates a delay element DLY for waiting the time from when a memory address is set in the memory address register MARI1 until the contents of the storage unit MEM are read out according to the memory address and the value is determined on the data line. .

7 is a shifter that functions as a delay for waiting the time from when a memory address is set in the memory address register MAR2ll until the contents of the storage unit MEA3 are read out according to the memory address and the value is determined on the data line. This is a register SFT.

In this embodiment, this shift register SFT7 has n bits, and a pulse input 8 is always added to its clock terminal CK at time intervals of t, so that when the flip-flop F/Fl4 has a value of ``0'', the shift register SFT7 The value of the flip-flop F/F25 added to the D terminal is taken into the shift register SFT7 and sent to the output terminal Q sequentially at time intervals of t.
shifted to the side. When the flip-flop F/Fl4 has the value ゜゛1゛, the shift register SFT7 has the input terminal D.
is forcibly cleared regardless of the value added to the clock terminal and the pulse input to the clock terminal.
The clear state is maintained while Fl4 is at the value "1". 9 is a selector SLCT9, and a flip-flop F/F1=
4'F'', the contents of the memory address register MARll are supplied to the memory unit M3 as a memory address, and when the flip-flop F/F1="゜0゛", the contents of the memory address register MAR22 are supplied as the memory address. It is supplied to the storage unit MEM3.

10 is a memory data register MD on the memory read source 1 side.
The value read from the storage unit MEM3 at Rl is set here.

11 is a memory data register MDR2, and the value read from the storage unit M3 is set here.

12adrs2 and 13adrs2 are the input lines of memory address registers MARl and MAR2, respectively, and 14ma
r, 15mar2 are memory address registers M
ARl, MAR2 output line, 16mar1set, 17
mar2set is each memory address register MA
This is the line on which the three data set signals for Rl and MAR2 are carried, and these signals also set the value "1" to the flip-flop F/Fl4 and flip-flop F/F25, respectively.
゛ is set.

18 adrsm and 19 atam are the memory address 4' address line and zeta line for the storage unit MEM3, respectively.

20maend1 and 21maend2 are storage units M
This is a memory read end signal when memory read is performed from memory read source 1 and memory read source 2 for EM3, respectively.

In this embodiment, memory read source 1 has a high priority. Next, the operation when a read request is generated from the memory read source will be explained.

7(1) When a read request is generated from memory read source 1, first, the contents of Adrsll2 are changed to Marlsetl6.
The signal sets the memory address register MARll, and at the same time the value '
6r1 is set.

Since F/F1="r', Marll4 is selected by the selector SLCT9, and this value becomes Adrsml8 and is added as a memory address to the storage unit MEMl8, and reading is started. The delay element DLY6 works, and the data is written on 7datam19. After waiting for the read value to be confirmed, its contents are set in the memory data register MDRllO, and at the same time, the value "゜0゛" is set in the flip-flop F/Fl4, and the memory access end signal Ma is set.
endl2O is issued. In the above reading process,
Flip●Flop F/F25 value is selector SLCT
Therefore, memory read source 1 can read without being influenced by memory read source 2. (Ii) When a read request is generated from the memory read source 2 and no read request is generated from the memory read source 1 until the read is completed, the contents of Adrs2l3 are first set to the memory address registers M and AR22 by the Nlar2serl7 signal. and flip at the same time●
The value "1" is set in the flop F/F25.

Since F/F1="0", selector SLCT9 selects Mar2l5, this value becomes Adrsml8, is added to storage unit MEM3 as a memory address, and reading is started.Flip-flop F/F
Since the value 46r' of 25 is added to the input terminal D of the shift register SFT7, the value of the shift register SFT7 changes from n bits 000...00,100 every time t according to the pulse input from the clock terminal CK.・・00,110
...00,111...00,...,111...1
Transition to 0, 111...11 and shift register SFT7
The output terminal Q of changes from the value ゜゜0゛ to the value "゜1゛,"
At that time, the contents read from the memory unit MEM3 to Dataml9 are set in the memory data register MDR22, and the value ゜"0" is set in the flip-flops F/F2 and F5.
is set, and the memory access end signal Maend
22l is served. (Iii) When a read request is generated from the memory read source 2, and before the read is completed, a read request is generated from the memory read source 1.Similar to (Ii), the contents of Adrs2l3 are transferred to the memory address register MAR22 by the Mar2setl7 signal. At the same time, the value "1" is set in the flip-flop F/F25.

At this time, if a read request has already been generated from memory read source 1, flip-flop F/F1=4'F3, shift register SFT7 is kept in the clear state, selector SLCT9 selects Marll4, and first Reading from memory access source 1 is performed. Also, if no read request is generated from memory read source 1, F/F1
="0", the selector SLCT9 selects Mar2l5, and this value becomes Adrsml8 and the memory unit M
It is added to EM3 as a memory address and reading is started. As described in (Ji), shift register SF
The value of T7 is 000...00,100...00,11
0...00,... If a read request is generated from the memory read source 1 during this process, the flip-flop F/F1 becomes ゜゛1゛, the shift register SFT7 is cleared, the selector SLCT9 selects Marll4, and the process is performed as described in (1). The contents of storage unit MEM3 are read and set in memory data register MDRllO. At the same time, flip ● flop F/F
Since the value "0" is set to 1, the shift register SFT
7 is released from the clear state, and selector SLCT9 becomes M.
Select ar2l5 and change the value of shift register SFT7 to 000...00,100 as described in (Ii) again.
...00,110...00,111...00,.
・, 111...11 and shift register SFT7
The output terminal Q of is shifted from the value "0" to the value "1", and the contents read from the storage unit MEM3 are set in the memristor register MDR2ll. As described above, according to the present invention, a memory read source with a high priority always reads the contents of a storage unit at the highest read speed inherent to the storage unit without being influenced by a memory read source with a low priority. I can put it out.

Further, since memory reading can be started for a memory read source with a low priority immediately after the memory read from a memory read source with a high priority is completed, the memory read time is also maximized. In the above embodiment, a shift register is used as a timer corresponding to a low priority memory read source, but any delay unit that can be kept in a clear state by a specific signal may be used.

Further, the storage unit is not limited to a random access memory or the like, but can be applied to any sharable device that can obtain an output signal after a predetermined time has elapsed in response to an input signal.・Brief explanation of the drawings FIG. 1 is a block diagram showing an embodiment of the present invention.

1, 2...Memory address register, 3...Storage unit, 4,5...Flip-flop, 6...Delay element, 7...Shift register, 9...Selector, 10, 11...Memory address register.

Claims (1)

[Claims] 1. In an apparatus in which a first memory read source and a second memory read source share a storage unit, and in which memory reads from the first memory read source are given priority over memory reads from the second memory read source, a timer configured to set a time until data read from the storage unit by a memory read from a memory read source is valid on a read line; and means for resetting the timer until memory reading by a first memory reading source is completed when a request is made.