JPS6046893B2 - Stop signal generation circuit for automatic tuning receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a stop signal generation circuit for an automatic tuning receiver, and particularly to an improvement for increasing the reliability of its trigger operation and reducing costs.

For example, as shown in FIG. 1, a stop signal generation circuit in a conventional automatic tuning receiver amplifies an intermediate frequency signal from a front end circuit 1 to a certain level in an intermediate frequency amplifier 2, and then picks up and extracts a part of the signal. , a trigger amplifier 3 performs narrowband amplification to obtain a trigger signal for stopping the automatic tuning receiver.

However, such a conventional circuit configuration requires a large number of parts and requires a great deal of effort to stabilize the trigger operation.

Furthermore, it is inevitable that the cost will be high due to the above-mentioned relationship between the number of parts and labor.

In FIG. 1, 4 is an FM detection circuit, and 5 is a multiplexer circuit. The present invention has been made in order to eliminate the drawbacks of such conventional circuits, and includes a means for inverting a DC voltage that changes linearly with respect to an antenna input level, and a low level in a predetermined frequency range centered around an intermediate frequency during reception. and means for generating a trigger signal for stopping the tuning operation of the automatic tuning receiver, which becomes high level only when the inverted DC voltage and the low level signal are simultaneously applied. do.

The present invention will be further explained with reference to the embodiments shown in the drawings. In FIG. 2, R is a semi-fixed resistor that sets the antenna input level to stop the tuning operation of the automatic tuning receiver, and Cl is an AC signal filter. The capacitor E is the DC voltage applied to the first input terminal 1, which changes linearly with respect to the antenna input level ANT, as shown in FIG. 3, and Q is the inverter transistor for inverting this DC voltage. , Q2 and σ are switching transistors, D1
12 is an interference prevention diode to prevent interference with an AM trigger signal from another circuit (not shown), and 12 is a voltage E with frequency characteristics as shown in FIG. 4, which is generated from the detection output of the FM detection circuit. .

The second input terminal o to which is applied is an output terminal of a trigger signal (stop signal) Eo for stopping the operation of the automatic tuning receiver. Note that the signal E.

It has become common practice in FM receivers to obtain . For example, Figure 2 C1 of Japanese Patent Publication No. 49-33882
Figure 2 of Special Publication No. 51-48011 C1 Special Publication No. 53-1
The signal corresponding to FIG. 4 described on the FIG. 2 opening of the 828 trowel may be applied to the second input terminal 12 as E2. In the circuit described above, the resistor R1 determines the operation start value of the transistor Q1 according to the antenna input level ANT, and when a DC voltage of about 0.6 V or more is applied to the first input terminal 11, the transistor Q1 is on, transistor Q2 is off, and its collector ●
The level will be high. On the other hand, as shown in FIG. 4, the voltage E2 applied to the second input terminal 12 is at a low level in a narrow frequency range of ±50 K pressure around the intermediate frequency of 10.7 M pressure during reception.

Therefore, when this low level voltage E2 is applied to the second input terminal 12, the collector level of the transistor O becomes high level, and the trigger signal E. is maintained at a high level. As shown, the collectors of the transistors Q2 and Q3 are directly connected to each other, and a combined output of the respective collector outputs appears at the output terminal 0, and becomes the trigger signal EO.
Therefore, if the base inputs of transistors Q2 and Ql3 are at high level, trigger signal E is generated. is of course at a high level.
On the other hand, when the DC voltage E1 is at a low level that cannot drive the transistor Q1, and when the voltage E2 causes a tuning shift, the transistors Q2 and Q3
The collector output of becomes low level and trigger signal E.

is at a low level, so no stop signal appears at output terminal 0. As explained above, according to the present invention, when setting the trigger level for the antenna input, this circuit and the third
By using it in combination with the FM-1F integrated circuit having the frequency characteristics shown in the figure, it is possible to simplify the automatic tuning receiver stop trigger circuit and facilitate trigger level adjustment. The range of variation due to adjustment of the set of is reduced.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the main parts of the automatic tuning receiver, Figure 2
FIG. 3 is a circuit diagram showing an embodiment of the present invention, FIG. 3 is a curve diagram showing the relationship between the antenna input ANT and the DC current, and FIG. 4 is a curve diagram showing the frequency characteristics of voltage (2). Q1: Inverter transistor, Q2, Q3: Collector directly connected switching transistor, R1: Semi-fixed resistor for level setting, 11: First input terminal, 12: Second input terminal, 0: Output terminal.

Claims (1)

[Scope of Claims] 1. Means for inverting and outputting a DC voltage that changes linearly with respect to the antenna input level, and means for receiving a signal that has a low level in a predetermined frequency range around an intermediate frequency during reception; Stop signal generation for an automatic tuning receiver, characterized by comprising a trigger signal generation means for stopping the tuning operation of the automatic tuning receiver, which becomes high level only when the above-mentioned inverted DC voltage and the low level signal are applied simultaneously. circuit. 2. The circuit according to claim 1, wherein the trigger signal generating means comprises two transistors whose collectors are directly connected.