JPS6046859B2 - Variable length coding serial transmission method - Google Patents

Abstract

PURPOSE:To make easy synchronism and to enable to delivery of high fidelity, by setting the bit length depending on the probability of occurrence per a given time of the level of the sampling time difference before and after the audio signal. CONSTITUTION:After the audio signal is sampling-held 2, the difference between the value of sampling time and that before it is obtained at the subtraction circuit 7, and the difference is A/D converted 3 and is synchronizingly mixed 12 with the pulse from the timing control circuit 13 via the parallel serial conversion and uneven length conversion circuit 10 and buffer memory 11, and the variable length cade of the bit length corresponding to the output level of the circuit 7 is delivered. Furhter, the output level of the subtraction circuit 7 shortens the bit length with comparatively smaller level having greater probability of occurrence per a given time and makes longer with comparatively greater level having smaller probability, performing coding.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for serially transmitting data using variable length coding, and particularly aims to provide a method that is easy to synchronize and is practical.

Conventionally, as for encoding methods, methods using variable length codes have been proposed in contrast to those using fixed length codes.

Encoding methods using variable-length codes include encoding methods that reduce redundancy from the perspective of level distribution using entropy encoding devised by Shannon, Hoffman, and Juano, or temporal correlation using DPCM etc. There are encoding methods that reduce redundancy and then use various error correction codes. However, these encoding methods have many problems when applied to high-fidelity transmission of audio signals, video signals, etc., making them difficult to put into practical use. In other words, in a data serial transmission method using fixed-length codes, the frame synchronization signal inserted in order to suppress the influence of code errors that may occur through the transmission path to a finite length has a constant period. Although it is easy to detect the signal, in the serial data transmission method using variable length codes, the code length of each word changes, so the inserted frame synchronization signal does not have a constant period. It is difficult to detect the frame synchronization signal, and the circuit size also has to be increased.

The present invention takes the above-mentioned points into account and proposes a variable length coding serial transmission method that is suitable for high-fidelity transmission and is easy to synchronize.

To explain the present invention below, FIG. 1 shows an example of a transmission system of a variable length coding serial transmission system to which the present invention is applied.

In FIG. 1, 1 indicates an input terminal to which an analog signal such as an audio signal is supplied, 2 indicates a sampling and hold circuit for sampling this audio signal, and 3 indicates an oil converter. The AD converter 3 is of a comparison type, and includes a comparison circuit 4, a control logic circuit and register 5 to which the output of the comparison circuit 4 is connected, and an oil converter 6 to which the output of this register is supplied. The output of the DA/converter 6 is supplied to a comparator circuit 4, where the level is compared with the input signal. For variable length encoding, the difference between the sampling time value appearing in the output of the sampling hold circuit 2 and the previous sampling time value is obtained in the subtraction circuit 7, and this difference is subjected to oil conversion.

In this example, pigeon converter 3 is used as the value of the previous sampling time.
The output of the DA converter 6 is used, and the output of the DA converter 6 is supplied to a subtraction circuit 7 via a delay circuit 8 such as an integrator. In this case, since the output of the DA converter 6 is a difference, the adder 9 is used to restore the original value. The output of this pigeon converter 3 is supplied to a parallel-to-serial conversion and unequal length conversion circuit 10, and further supplied to a synchronous mixing circuit 12 via a buffer memory 11. The frame synchronization signal is generated from timing control circuit 13. The timing control circuit 13 also generates sampling pulses for the sampling hold circuit 2 and clock pulses for the AD converter 3 and the parallel-serial conversion and unequal length conversion circuit 10. In this way, a variable length code having a bit length corresponding to the level of the output of the subtraction circuit 7 is obtained at the output terminal 14. This is then sent out to the transmission path. As shown in FIG. 2, the reception system includes a buffer memory 16 connected to the input terminal 15, a serial-parallel conversion and equal-length conversion circuit 17 to which the output of the buffer memory 16 is supplied, a DA converter 18, and a deglitch switch. It is composed of a circuit 19 and a timing control circuit 21 which forms clock pulses for these circuits based on a frame synchronization signal separated by a synchronization separation circuit 20.

Since the output of the deglitch circuit 19 is a difference, the output of the adder 22 and the delay circuit. 23 to restore the original level, and a demodulated audio signal can be obtained at the output terminal 24. The level of the output of the subtraction circuit 7 in the above-mentioned transmission system has a probability of occurrence per predetermined time as shown in FIG. The distribution will be as follows.

The horizontal axis in FIG. 3 shows the output level of the subtraction circuit 7, and the vertical axis shows the probability of occurrence. As is clear from this figure 3,
For example, in an audio signal, the level rarely increases (positive direction) or decreases (negative direction) during one sampling period. Therefore, if the signal with a higher probability of occurrence or signal with a lower level is encoded with a shorter bit length, and the signal with a lower probability of occurrence or signal with a higher level is encoded with a longer bit length, it is possible to minimize redundancy and achieve high fidelity. It becomes possible to transmit information at high speeds. FIG. 4 shows an example of a variable length code according to the present invention. In Figure 4, the analog signal (difference level) is quantized to 233 degrees in the positive and negative directions, encoded into a 13-bit folded linear code by an AD converter, and then further converted into a variable length code. ing. A feature of this variable length code is that one word is formed by a predetermined number of units of fixed length, for example, 4 bits (hereinafter referred to as segments) including identification bits. As an identification bit included to express the connection relationship with each segment, for example, the first bit of one word (referred to as the word-initial bit) is set as "゜0゛." 1 bit (referred to as connection bit)
is set as ゜゜1゛. Further, the sign bit for determining whether the word is positive or negative is the 1 bit following the initial bit of the word, and the sign bit is set as "゜1゛" when the word is positive, and "゜0゛" when it is negative.
Therefore, to explain only the positive side, when one word length is 4 bits, there are 2 valid data bits other than the initial bit or connection bit, which is an identification bit, and the sign bit. It is possible to encode a level range of 3, and when one word length is 8 bits, the effective data bits are 5 bits, so in the figure, a level range of 4 to 35 can be encoded. I can do it,
Similarly, when one word length is 12 bits, the effective data bits are 8 bits, so in the same figure, 36 to 291
Furthermore, when one word length is 16 bits, the effective data bits are 11 bits, so in the same figure, the level range from 292 to 2339 can be encoded. I can do it.

When transmitting such a variable length code, frame synchronization pulses are inserted at predetermined intervals of consecutive segments.

The next bit of the first frame synchronization signal is the beginning bit '4
The code of one word can be distinguished by detecting whether the fourth bit is "1" or "0". In this way, the variable-length coded serial transmission method according to the present invention can be considered in exactly the same way as a fixed-length code from the point of view of frame synchronization, making it easy to detect frame synchronization signals, and making it easier to detect disturbances from the transmission system. can be made stronger. Of course, the variable length has the advantage of minimizing redundancy without sacrificing fidelity. FIG. 5 shows another example of the present invention, in which one segment has a length of 4 bits as in the case of FIG. 4, and includes an initial bit or connection bit which is an identification bit, and a sign bit. However, in order to simplify the configuration for unequal length conversion, the code is converted to one with the same bit configuration as the folded linear code.

Also, if you do this, for example, [00001000]
Since the code does not mean any information, it can be used as a space when the transmitting buffer memory underflows. If such a space is used appropriately, the receiving system, which has a buffer memory of the same capacity as the transmitting system (extra capacity for correcting time axis fluctuations is required), will not overflow. It will be clear that the example shown in FIG. 5 also has advantages similar to those described above. In addition,
Although not shown, as a special feature of the pigeon converter, the analog input signal is divided into multiple level ranges depending on the level, and AD
There is something that can be converted.

To DA convert an AD-converted signal in this way, a range bit indicating a gain is received together with an output code, and the DA-converted analog output signal is passed through an amplifier with a gain specified by the range bit. Just do it. Such a method has the advantage of being able to AD convert an analog signal with a wide dynamic range with a small number of bits, and is called polygonal quantization or nonlinear AD conversion. The present invention can be applied to such non-linear AD conversion, and in that case, there is an advantage that the same information as the range bits is expressed by the number of segments, so that no special range bits are required.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an example of a transmitting system used to implement the present invention, Fig. 2 is a block diagram of an example of the receiving system, Fig. 3 is a diagram used to explain the present invention, and Fig. 4 is a block diagram of an example of the receiving system. FIG. 5 is a route map used to explain another example of the present invention. 1 is an analog signal input terminal, 3 is an AD converter, and 18 is a DA converter.

Claims (1)

[Claims] 1 converting the signal to be transmitted into a series of variable length coded words and forming each of said series of variable length coded words by a predetermined number of segments having a constant bit length, each of said segments Formed from data bits and identification bits for identifying the beginning of a word or a break from other segments, frame synchronization is performed every predetermined number of consecutive segments when transmitting the series of variable-length encoded words. A variable length coding serial transmission method that adds signals.