JPS6046740B2 - signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal processing device such as a control device or a monitoring device that has an arithmetic unit with a computer function and a relay unit.

In FIG. 1, the relay section 10 includes contacts 13 of an electromagnetic relay (hereinafter referred to as relay) that opens and closes external power supplies 11 and 12;
Relays 15 and 16 receive the input signal through relay 14, and transmit the input signal to calculation unit 17 through their respective contacts 15a and 16a.

Further, in the relay section 10, relays 18 and 19 receive an output signal from the calculation section 17, and open and close external power supplies 20 and 21 through their respective contacts 18a and 19a, thereby supplying power to loads 22 and 23. The arithmetic unit 17 is a C
A digital input module 26 (hereinafter referred to as DI) and a digital output module 2 are connected to the PU 24 and the common bus 25.
7 (hereinafter referred to as Kyogen), and the relay section 10
The signal from D027 is received by DI26, and the signal from D027 is sent to relay section 10.

The relay section 10 and the calculation section 17 are connected by a cable 28 between a connector CNI (hereinafter simply referred to as CNI) and a connector CN2 (hereinafter simply referred to as CN2).

1 If a failure occurs in such a configuration, for example, even though the external power supply 11 is normal and the input signal is coming to the relay 15 due to the relay contact 13 being closed, the CPU 2
4 reads the status of DI26 and determines that no signal is coming to the 0th bit of DI26, the cause is thought to be either relay 15 or DI26 (CP
Abnormalities in U can be determined by a watchdog, etc., and C
In this case, it is assumed that there is no failure in the cable between Nl and CN2).

For example, if the relay 19 does not operate even though it is outputting to the first bit of CPUPO27, DO2
It is thought that either relay 7 or relay 19 is the cause. In such a case, the general fault finding method is to disconnect the cable between CNl and CN2 and apply an input signal to the 0th bit of DI26 using an external tester to check whether DI26 is positive or abnormal, or to check whether DI26 is positive or abnormal. Receive the signal from the 1st bit with an external tester and check whether DO26 is positive or abnormal.

With this method, it is troublesome and time consuming to disconnect the cable between CN1 and CN2, use an external tester, and find the cause of the failure.

SUMMARY OF THE INVENTION An object of the present invention is to provide a signal processing device that eliminates the above-mentioned drawbacks and makes it possible to easily discover whether the cause of a failure is caused by the relay unit or the arithmetic unit. The present invention will be explained below with reference to FIGS. 2 and 3.

As shown by the dotted line in FIG.
Diagnosis of whether the bit is correct or abnormal is performed using the 2nd and 3rd bits of DO27, and diagnosis of whether the 0th or 1st bit of DO27 is correct or abnormal is performed using the 2nd and 3rd bits of DI26. You can use any check bit as long as it does not overlap with the input/output bits.) FIG. 2 shows the case of failure diagnosis of DI26.

The contact 15a of the relay 15 of the relay section 10 is connected in parallel with the open collector transistor 29 at the output section of the DO 27, and when the transistor 29 is made conductive via the photocoupler 30 by a command from the CPU 24, the DI 26
If is normal, the current flows through the diode of photocoupler 31→
The current flows from the resistor 32 to the transistor 29, and a current flows to the photo side of the photocoupler. A signal is generated at point A and IC33 (TC5
The signal at point A is read into the CPU 24 through OL2P).

FIG. 3 shows the case of failure diagnosis of DO27.

When PO 27 is made conductive by a command from CPU 24 (in this case, (1) is normal), a signal is generated at point B through the same current path as described above, and the signal is read into CPU 24 through IC 33. In the above explanation, CP
Instructions from U24 are executed by the test program.

As explained above, the present invention always changes the output of DO27 to D.
Check the input of DI26 with DO27.
In this case, the signals to be checked are the input/output signals between the relay section 10 and the calculation section 17, regardless of the input/output signals of the relay section 10, and when a failure occurs, Immediately determine whether the failure occurs in the arithmetic unit or the relay unit.

Therefore, the time required for troubleshooting can be greatly shortened, and unit replacement can be carried out smoothly, which is extremely effective.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram consisting of a relay section and an arithmetic section to which the present invention is applied, and FIGS. 2 and 3 are circuit configuration diagrams showing one embodiment of the present invention. 10... Relay part, 11, 12... External power supply, 13, 14... Contact, 15, 16...
・Relay, 17... Arithmetic unit, 18, 19...
...Relay, 20, 21... External power supply, 22,
23...Load, 24...CPU125...
... Common bus, 26 ... Digital input module, 27 ... Digital output module, 28
...Cable, 29...Transistor,
30, 31...Photocoupler, 32...
·Resistor.

Claims (1)

[Claims] 1. A relay unit that receives an external input signal through an input relay and receives an internal input signal through an output relay, a digital input module, a digital output module, and a central processing unit (CPU), and a contact signal of the input relay of the relay unit. is input to the central processing unit (CPU) via the digital input module and subjected to predetermined signal processing, and the processed signal is applied to the output relay of the relay unit via the digital output module and the contact signal is output to the outside. In a signal processing device configured to extract a signal, a signal to the digital input module is introduced to the digital output module, and a signal from the digital output module is introduced to the digital input module, so that the signal from the digital input module and the A signal processing device comprising means for checking input/output signals with a digital output module.