JPS6046463B2 - Waiting control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a queuing control system for input/output device control commands in a central control unit.

In explaining the present invention, a schematic system configuration diagram thereof is shown in FIG.

In FIG. 1, a central control device 100 and each terminal device 11
0, 111 to 11n are address buses A0 to A7,
They are connected to each other via an input device control bus IN) and an output device control bus OUT) data buses D0 to D7. When the central control device 100 executes the input/output device control command,
When address information is transmitted via the address buses A0 to A7, the terminal equipment uses the address buses A0 to A7 to
Terminal device 11 that matches the terminal device Aha Geki X (number)
Only 0 is controlled. Conventionally, there is a system shown in FIG. 2 as this type of waiting control system. In FIG. 2, when the central processing unit 210 of the central control unit 200 executes an input device control command, the IN terminal becomes low level, and when the output device control command is executed, the OUT terminal becomes low level, and the two terminals are The output of the AND gate 250, which is used as an input, changes from a high level to a low level because one of the inputs becomes a low level when an input/output device control command is executed. A differentiating circuit including an inverter 204, a low resistor 205, a capacitor 206, and a NOR gate 203 that detects this fall (change from high level to low level) sends a clear signal to the waiting control counter 202, and outputs D of the waiting control counter 202. changes from high level to low level. The output D of the rendezvous control counter 202 is connected to the rendezvous control terminal RDY of the central processing unit 210, and the output D of the counter 202 becomes high level, canceling the rendezvous request signal to the central processing unit 210. The CP terminal of the waiting control counter 202 is connected to the basic clock terminal CLK of the central processing unit 210 via the OR gate 201, and when the basic clock performs counting and addition, and the output D of the waiting control counter 202 becomes high level, The output of the OR gate 201 remains at a high level, and no further counting is performed even if the basic clock arrives. In other words, the time from when the output terminal D of the waiting control counter 202 goes low to when it goes low is the waiting time of the central processing unit 210.

Here, in order to provide a waiting time for stable control when the central processing unit 210 executes an input/output device control command for a terminal device, it is necessary to It is necessary to set the waiting time based on the maximum delay time, taking into account the propagation delay time related to the distance between the central processing unit 210 and the terminal equipment, and set the count addition value of the waiting control counter 202. here,
As mentioned above, the drawbacks of the prior art are that the central control unit 2
Even if the distance between 00 and the terminal device is short, the propagation delay time of each signal is small, and the delay time due to the integrated circuit in the terminal device is small, the waiting control counter is set at the waiting time that requires the longest delay time in the entire system. Since the waiting time value 202 is set, the central processing unit 210 cannot execute the next process unless the maximum waiting time automatically elapses.

That is, when the central processing unit 210 executes an input/output device control command for a terminal device for which a short waiting time is sufficient, there is a drawback that the invalidity (loss) time is large.
This has the disadvantage that it has a large effect on the processing time in the central processing unit 210 and is largely attributable to a decrease in processing capacity.

In addition, the central control unit 200 may
central control unit 2 even if it is excluded from the control bus of
00 had the drawback that an input/output device control command was executed for the terminal device even though the terminal device did not exist. The purpose of the present invention is to eliminate these drawbacks, provide a means that can detect the delay time between the central control unit and each terminal device for each terminal device, and make it possible to invalidate only the delay time of each terminal device as the waiting time. This reduces the amount of time it takes for the central control unit to operate, improving the processing capacity of the central control unit, and at the same time detecting terminal devices that are not under the control of the central control unit in advance and disabling them. The purpose of the present invention is to provide a queuing control system that takes into consideration accurate and more detailed input/output control by not executing input/output device control commands.

In order to achieve this purpose, the waiting control method of the present invention is such that, in the embodiments of the present invention described later, the central control unit issues input/output device control commands only to selected terminal devices from among the plurality of terminal devices under its control. In a system that executes the above, in a waiting control method that controls a waiting time until data import and data retrieval is performed after an input/output device control command controlled from the central controller, the system is provided in the central controller. means for adding and transmitting a terminal device address while the central processing unit is not executing an input/output device control command, and a time value until a response signal from the terminal device matching the terminal device address is returned. Each time an input/output device control command is executed for a terminal device, the waiting time value is read out and subtracted from the means for counting and storing the waiting time value for each terminal device. The system is configured to include means for determining a waiting time, and means for not executing the input/output device control command for a terminal device whose time value stored in the means exceeds a predetermined fixed time value. . A feature of the present invention is that a bus for detecting waiting control time is provided independently of the control signal bus of the central processing unit. It is output based on the value of the counter that is incremented during the execution of the control command (while executing the control command), and the time until the terminal device with the terminal device address that matches the counter value responds is stored in the memory in the central control unit. The time value corresponding to the contents of the memory is set as the waiting time value when the central processing unit executes an input/output device control command to the terminal device, and the data between the central control unit and the terminal device is stored. By detecting the transfer delay time, only the delay time necessary for each terminal device is set as the waiting time, reducing the invalid time of the central control unit so that the processing capacity does not decrease, and further reading the memory. The central processing unit executes input/output device control commands to the terminal device until it detects a terminal device that has been disconnected from the bus of the central control device and connects the terminal device to the bus again. The processing capacity of the central processing unit is improved even if invalidation processing is not performed.
Next, an embodiment of the present invention will be described using FIGS. 3 and 4.

FIG. 3 is a system configuration diagram of an embodiment of the present invention, where 300 is a central control unit and 310, 311, . . . , 31n are terminal devices.

In FIG. 3, the central control device 300 includes a terminal device 31
0, 311 . When the central control device 300 outputs a device address that matches the terminal device address on the bus of TAO to TA7 through its internal processing, only the terminal device that matches the address sends the terminal device address to the central control device 300. The response information is output via the response response bus ANS, and the input device control command is IN, the output device control command is 0UT, addresses AO to A7, data DO to D7, and each terminal device is 310-31n. Next, the present invention will be explained in detail with reference to FIG.

In FIG. 4, the central control device 300 in FIG.
Corresponding to the terminal device 310 is a central control device 400 and a terminal device 410. When the central processing unit 420 including the central processing unit 400 is not executing an input/output device control command, that is, when executing a memory control command, the MEMR (memory read command) and MEMW (memory write command) of the central processing unit 420 are executed. When the output of any one of the commands becomes high level, the output of the OR gate 436 also becomes high level, and one input of the AND gate also becomes high level. Here, if the upper addresses A8 to Al5 of the memory control commands are all other than high level, the output of the NAND gate 438 becomes high level, and the other input of the AND gate 437 also becomes high level, The output also becomes high level.
Next, a NAND gate 4 receives the high-level STSTB signal output at each instruction break (in other words, output at the beginning of each instruction) and the output of the AND gate 437.
The output of 21 becomes low level, and the output of flip-flop 42
Change the output 0 of 2 from high level to low level. The terminal device address generation counter 423 at the next stage, which receives this change from high level to low level as input, performs counting and addition. The output of the terminal device address generation counter 423 forms a terminal device address generation bus 425 from output terminals TAO to TA7 of the central control unit 400 via a buffer gate 424. Next, when an address that matches the device address of the terminal device 410 is output on the terminal device address generation bus 425, the terminal device 410 outputs a low level on the terminal device address-match response bus 426. Central control device 40
0 is input to the receiver gate 427 via the ANS terminal.The output of the receiver gate 427 is input to one side of the AND gate 428, and when the output becomes low level, the waiting time count addition counter 42
The count addition value of 9 is accumulated in the waiting time temporary accumulation register 430.

The CL terminal of the waiting time counting addition counter 429 is connected to the output 0 of the flip-flop 422,
When the output 0 of the flip-flop 422 changes from high 7 level to low level, the CL terminal of the waiting time counting addition counter 429 also becomes low level, and counting and addition starts in synchronization with the basic clock coming from the central processing unit 420. . Next, the output of flip-flop 422 is 0
By changing from high level to low level,
At the same time as the terminal equipment address generation counter 423 is counted and added, the waiting time counting and addition counter 429 is also counted and added in synchronization with the basic clock of the central processing unit 420, and the added value is transferred from the terminal equipment 410 to the terminal. When a low level response signal arrives on the device address match response bus 426, the waiting time is simply stored in the temporary storage register 430. The waiting count addition value accumulated in the register 430 uses the output of the terminal device address generation counter 423 as one input, and
Other inputs are data buses DO to D7 of the central processing unit 420.
A queue processing circuit 433 is stored in a random access memory 432 whose address is the output of a selector 431 connected to
Written under the control of

Here, the queuing processing circuit 433 uses the AND gate 42 to store information accumulated in the queuing time temporary storage register 430.
If the central processing unit 420 is not executing an input/output device control command as detected by the LD input connected to the output of selector 4 while the MREO terminal is at a high level,
31, the output of the terminal device address generation counter 423 is used as the address input of the random access memory 432, and the output of the temporary waiting time storage register 430 is used as the data retrieval input to perform write control.

As a result, the waiting time for each terminal device is stored in the random access memory 432. Upon completion of the write process to the random access memory 432, the waiting processing circuit 43
3 makes the output 0 of the flip-flop 422 a high level by outputting a low level from the S terminal, but
At this time, the other input terminal R of the flip-flop 422
Even if a low level falls from the NAND gate 421, the output 0 of the flip-flop 422 remains at a high level, thereby preventing malfunction.

Here, since the output 0 of the flip-flop 422 becomes high level, the output of the buffer gate 424 becomes high impedance. Therefore, all of the terminal device address generation buses 425 become high level.

Since the configuration is such that there is no terminal device address in which all bits are high level, no terminal device sends a low level onto the terminal device address match response bus 426 and becomes high level.

The fact that the terminal device address-match response bus 426 becomes high level is transmitted to the receiver gate 427 and the AND gate 428 via the ANS terminal of the central control unit 400, and then to the DL terminal of the rendezvous processing circuit 433. The waiting processing circuit 433 changes the low level output of the S terminal to high level when the LD terminal changes from low level to high level.

Next, if the central processing unit 420 does not execute the input/output device control instruction and is the first instruction, the MEMR
Terminal or MQr! The 4w terminal and the STSTB terminal become high level, the output of NAND gate) 42 becomes low level, and the contents described at the beginning of this explanation are continued.
The contents of the random access memory store the waiting times for all terminal devices. Next, the central processing unit 420
When executes an input/output device control instruction/instruction, the MEMR signal,
Both MEMW signals are at low level, and the OR gate 436
and the output of the AND gate 437 are also at a low level, the gate of the selector 31 is also at a low level, and AO to A7 of the central processing unit 420 are selected for the output.

The AO to A7 outputs of the central processing unit 420 become the addresses of the random access memory 432, and at the same time
The input/output device control command and the terminal device address to be executed are supplied to the terminal device via the B-AO7B bus.

The terminal equipment waiting time value corresponding to the address of random access memory 432 is output from terminals DOO to DO7 of random access memory 432.

This value is added by a count (countdown) connected to the output of an AND gate 435 that becomes low level when either the output device control command execution signal 10W or the input device control command execution signal 10R of the central processing unit 420 is executed.
The LD terminal of the counter 434 causes the same count to be input into the subtraction counter 434. The counting addition counter 434 is decremented in synchronization with the basic clock coming from the CLK terminal of the central processing unit 420.

The central processing unit 420 is connected to the borrow terminal BR of the counting subtraction counter 434 via the inverter 436, so that the counting subtraction counter 434 starts counting and the low level is reached from the borrow terminal BR. The central processing unit 420
The central control unit 420 is placed in a waiting state by setting the waiting control terminal RDY of the central controller 420 to a low level.

Next, the count subtraction counter 434 performs count subtraction,
When a low level is output from the pollo terminal BR, the output of the inverter 436 becomes a high level, and the queue control terminal RDY of the central controller 420 also becomes a high level, and the process progresses from the waiting state to the command execution state, and the terminal It is possible to execute input/output commands to the device.

This means that while the central processing unit 420 is not executing input/output commands, the input/output device control commands from the central controller are stabilized for each terminal device address that matches the input/output command address to each terminal device. A random access memory 432 is provided for storing an executable waiting time, and when an input/output command is executed, a waiting time is set according to the waiting value of the memory 432. Next, when an address where no terminal device exists is output on the terminal device address generation bus 425, a low level is output on the terminal device address-match response bus 426 from any terminal device. It doesn't come.

Therefore, the waiting time counting addition counter 429 changes the value of the waiting time counting addition counter 429 (all bits are at high level) only when a low level carry signal is output from the carry terminal CR. is accumulated in the waiting time temporary accumulation register 430. The waiting processing circuit 433 includes a waiting time counting addition counter 42.
A carry signal from 9 is received by the ALM terminal to write the contents of the waiting time temporary storage register 430 into the random access memory 432. As a result, when a certain terminal device is disconnected from various buses due to a failure or the like, all bits are stored at a high level in the random access memory 432 during the waiting time.

Here, if the central processing unit 420 periodically executes a memory read name instruction that changes one bit at a time among the lower memory addresses AO to A7 while the upper memory addresses A8 to Al5 are all at a high level, the central processing unit 420 Since addresses A8 to Al5 are at high level, the output of NAND gate 438 is at low level.
Since the output of the inverter 439 also goes to the high level according to the present invention (1), the output of the NAND gate 440 goes to the low level.

On the other hand, since the output of the NAND gate 438 is at a low level, the output of the AND gate 437 is at a low level, and the selector 431 selects the signals at the address AO to A7 terminals of the central processing unit 420, thereby controlling the random access memory. 432 data terminals DOO~DO
7 to the input terminal of the three status gate 441, and is connected to the output of the NAND gate 440. 440 becomes low level, the input information (waiting time value) of the three status gate 441 becomes the data input DO~D of the central processing unit 420.
7 and is taken into the central processing unit 420.

In this way, by periodically reading the contents of the random access memory 432, when the terminal equipment is disconnected from the control bus of the central control unit 400 due to a failure or the like, the contents of the random access memory 432 can be read out. This can be detected because all of the waiting time values are at a high level.

From the time when it is detected that the terminal device is disconnected from the control bus of the central control device 400, the contents of the random access memory 432 are periodically read again, and the terminal device is connected to the control bus of the central control device 400. By executing input/output commands to the terminal device and preventing it from executing invalidation processing until it is detected that the
Processing for all terminal devices is finely controlled.

As explained above, the present invention detects the waiting time required by the terminal equipment while the central processing unit is not executing input/output equipment control commands, and stores the waiting time value for each terminal equipment. Then, when the central processing unit executes an input/output device control command to a terminal device, it reads the waiting time value and sets a corresponding waiting time, thereby reducing the delay time required for each terminal device. It can be a waiting time.

This makes it possible to eliminate ineffective (loss) time of the central control unit, and to significantly improve processing efficiency.

In addition, when a terminal device is no longer under the control of the central processing unit, it is detected when the content of the memory exceeds a predetermined value, and the input/output device for the terminal device is detected. This has the advantage that fine control can be achieved even by not executing control commands.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram of an example of a conventional waiting control system, in which 100 is a central control unit and 110 to 11n are terminal devices. FIG. 2 is a circuit diagram of the main parts of an example of a conventional waiting control system, in which 200 is a central control unit, 210 is a central processing unit, 2
04 is an OR gate, 202 is a counter, 203 is a NOR gate, 204 is an inverter, 250 is an AND gate, 2
05 is a resistor, and 206 is a capacitor. FIG. 3 is a system configuration diagram of an embodiment of the present invention, where 300 is a central control unit and 310 to 31n are terminal devices. FIG. 4 is a circuit diagram of the main parts of the embodiment of the present invention, in which 400 is a central control unit, 420 is a central processing unit, 432 is a random access memory for storing waiting time, 424 is a bus driver, and 427 and 441 are bus receivers. (three status gate), 433 is a waiting processing circuit, 423, 429,
434 is a counter, 430 is a latch register, 438,
440, 421 is Nand Gate, 436 is Or Gate,
437, 435, 428 are AND gates, 436, 43
9 is an inverter, and 431 is a selector.

Claims (1)

[Scope of Claims] 1. In a system in which the central controller executes an input/output device control command only for a selected terminal device out of a plurality of terminal devices under the control of the central controller, the central controller In a waiting control method that controls a waiting time until data import and data retrieval is performed after the input/output equipment control command is controlled by a central processing unit provided in the device, the central processing unit executes the input/output equipment control command. means for counting and transmitting the terminal equipment address while not being executed, and storage means for counting and storing the time value until the response signal from the terminal equipment matching the plurality of terminal equipment addresses is returned. , comprising means for determining the waiting time by reading and subtracting the waiting time value from the means for adding and storing the waiting time value for each terminal device each time the input/output device control command is executed for the terminal device. Waiting control method. 2. In a system in which the central controller executes input/output device control commands only for selected terminal devices out of a plurality of terminal devices under the control of the central controller, a central processing unit provided in the central controller In a waiting control method that controls a waiting time until data import and data retrieval is performed after the input/output equipment control command controlled by the device, while the central processing unit is not executing the input/output equipment control command, means for counting and adding and transmitting a terminal device address; a storage means for counting and storing a time value until a response signal from a terminal device matching the terminal device address is returned; and means for not executing the input/output device control command for a terminal device whose read value exceeds a predetermined time value.