JPS6046039A - Bonding method of semiconductor element - Google Patents

Bonding method of semiconductor element

Info

Publication number
JPS6046039A
JPS6046039A JP58154328A JP15432883A JPS6046039A JP S6046039 A JPS6046039 A JP S6046039A JP 58154328 A JP58154328 A JP 58154328A JP 15432883 A JP15432883 A JP 15432883A JP S6046039 A JPS6046039 A JP S6046039A
Authority
JP
Japan
Prior art keywords
solder
semiconductor element
substrate
paste
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58154328A
Other languages
Japanese (ja)
Inventor
Shigeki Iguchi
茂樹 井口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP58154328A priority Critical patent/JPS6046039A/en
Publication of JPS6046039A publication Critical patent/JPS6046039A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3485—Applying solder paste, slurry or powder

Abstract

PURPOSE:To obtain an optimum method for automating with excellent mass productivity by forming a standoff on each electrode pad of a semiconductor element, coating solder paste on the wiring pattern of a substrate, positioning the element and the substrate, then filling them in a reflow furnace and bonding them. CONSTITUTION:A Cu standoff 2 is formed on each pad of an LSI chip 1, and a solder bump is not formed. Then, a solder paste 6 is screen printed on a wiring pattern 5 of a substrate 4. Here, it is desirable to coat only the paste 6 on the pattern 5, but since the solder particles in the paste 6 are approx. 0.1mm., the pitch of the pattern is limited to 0.3mm., and cannot be printed with the finer pitch smaller than this. In such a case, solder past is coated across the wirings 5. Thereafter, the chip 1 and the substrate 4 are positioned, filled in a reflow furnace 7, and heated by a heater 8 to bond them.

Description

【発明の詳細な説明】 く技術分野〉 本発明はソルダーペーストを用いた半導体素子のボンデ
ング方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a method for bonding semiconductor elements using solder paste.

〈従来技術〉 従来のＬＳＩチップボンデング方法は第１図（イ）及び
（ロ）に示す様に、ＬＳＩチップ１の電極パッドにメッ
キ法によりまずＣｕスタンドオフ２を形成し、その上に
半田バンプ３を形成する。<Prior art> As shown in FIGS. 1(a) and 1(b), the conventional LSI chip bonding method first forms Cu standoffs 2 on the electrode pads of the LSI chip 1 by plating, and then solders are applied thereon. A bump 3 is formed.

そして、半田バンプ３を基板４の配線パターン５に位置
合わせしたのち、ＬＳＩチップ１の上からヒータ６を押
し付け、加熱加圧してボンデングする。After aligning the solder bumps 3 with the wiring patterns 5 of the substrate 4, a heater 6 is pressed onto the LSI chip 1, and bonding is performed by applying heat and pressure.

しかしながら、このようなボンデング方法では、半田の
供給すなわち半田バンプの形成にメッキ法を用いている
ので、工程が煩雑で時間がかかり過ぎるため、量産性が
非常に悪く自動化することが出来なかった。However, in this bonding method, plating is used to supply solder, that is, to form solder bumps, so the process is complicated and takes too much time, making it extremely difficult to mass-produce and cannot be automated.

〈目　的〉 本発明はかかる従来方法の欠点に鑑みて成さｈたもので
、その目的とするところは、半導体素子の各電極パッド
にスタンドオフを形成し、基板の配線パターンにソルダ
ーペーストを塗布し、前記半導体素子と前記基板との位
置合わせを行なったのち、リフロー炉に入れてボンデン
グすることにより、量産性に優れ自動化に供して最適な
半導体素子のボンデング方法を提供することにある０〈
実施例〉 以下図にもとづいて本発明の詳細な説明する。<Purpose> The present invention was made in view of the drawbacks of the conventional method, and its purpose is to form standoffs on each electrode pad of a semiconductor element and apply solder paste to the wiring pattern of the board. The object of the present invention is to provide an optimal semiconductor element bonding method that is excellent in mass production and can be automated, by coating the semiconductor element and aligning the semiconductor element and the substrate, and then placing the semiconductor element in a reflow oven for bonding. <
Examples> The present invention will be described in detail below based on the drawings.

第２図（イ）〜に）は本発明のボンデング方法を説明す
る図である。FIGS. 2(a) to 2) are diagrams for explaining the bonding method of the present invention.

まず、ＬＳＩチップ１の各電極パッドにＣｕスタンドオ
フ２を形成する。（なお、ハンダバンプは形成しない。First, Cu standoffs 2 are formed on each electrode pad of the LSI chip 1. (Note that no solder bumps are formed.

） 次に、基板４の配線パターン５にソルダーペースト６を
スクリーン印刷する。ここで、同図（？）の如くソルダ
ーペースト６は各配線パターン５上にのみ塗布するのが
望ましいが、ソルダーペースト内のハンダ粒子は０．１
ｍｍ程度あるため、ソルダーペーストパターンのピッチ
は０．３咽が限度であり、これ以下の細かいピンチでは
印刷できない。このような場合は同図（ハ）の如く、各
リード配線５を横切ってソルダーペーストを塗布する。) Next, solder paste 6 is screen printed on the wiring pattern 5 of the board 4. Here, as shown in the same figure (?), it is desirable to apply the solder paste 6 only on each wiring pattern 5, but the solder particles in the solder paste are 0.1
Since the pitch of the solder paste pattern is approximately 0.3 mm, the pitch of the solder paste pattern is limited to 0.3 mm, and printing is not possible with a finer pinch than this. In such a case, solder paste is applied across each lead wiring 5 as shown in FIG.

その後、ＬＳＩチップ１と基板４との位置合ゎせを行な
い、同図に）に示す様にリフロー炉７に入れて、ヒータ
ー８で加熱しボンデングする。このとき、ハンダは表面
張力にょシ各リード配線５へ集中する。したがって、同
図（ハ）の如くリード配線５を横切ってソルダーペース
トを塗布しても短絡することなくホンデングすることが
出来る。Thereafter, the LSI chip 1 and the substrate 4 are aligned, placed in a reflow oven 7 as shown in the figure, and heated with a heater 8 for bonding. At this time, the solder concentrates on each lead wiring 5 due to surface tension. Therefore, even if the solder paste is applied across the lead wiring 5 as shown in FIG.

このように、半田供給が印刷によって短時間にできるの
で、工程が非常に簡略化され且量産性が著しく改善され
る。In this way, since solder can be supplied in a short time by printing, the process is greatly simplified and mass productivity is significantly improved.

く効　果〉 以上の如く本発明に係る半導体素子のボンデング方法は
、半導体素子の各電極パッドにスタンドオフを形成し、
基板の配線パターンにソルダーペーストを塗布し、前記
半導体素子と前記基板との位置合わせを行なったのち、
リフロー炉に入れてボンデングするようにしたから、量
産性に優れ、しかも自動化に供して最適な半導体素子の
ボンデング方法を提供することが出来る。Effects> As described above, the method for bonding a semiconductor element according to the present invention includes forming standoffs on each electrode pad of the semiconductor element,
After applying solder paste to the wiring pattern of the board and aligning the semiconductor element and the board,
Since the bonding process is carried out in a reflow oven, mass production is excellent and it is possible to provide an optimal bonding method for semiconductor elements that can be automated.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（イ）及び（ロ）は従来のボンデング方法を説明
する図、第２図（イ）〜に）は本発明に係る半導体素子
のボンデング方法を説明する図である。 ｌはＬＳＩチップ、２はスタンドオフ、４は基板、５は
配線パターン、６はソルダーペースト、７はりフロー炉
、８はヒーター 代理人　弁理士　福　士　愛　彦（他２名）ＣＡ）４′ 第 （４） （ハ） ダ ＣＯ”） １図 （ニ）FIGS. 1(A) and 1(B) are diagrams for explaining a conventional bonding method, and FIGS. 2(A) to 2(B) are diagrams for explaining a method for bonding a semiconductor element according to the present invention. 1 is an LSI chip, 2 is a standoff, 4 is a board, 5 is a wiring pattern, 6 is a solder paste, 7 is a beam flow furnace, 8 is a heater agent Patent attorney Aihiko Fuku (2 others) CA) 4' No. (4) (c) DaCO”) Figure 1 (d)

Claims (1)

【特許請求の範囲】[Claims] １、半導体素子の各電極パッドにスタンドオフを形成し
、基板の配線パターンにソルダーペーストを塗布し、前
記半導体素子と前記基板との位置合わせを行なったのち
、リフロー炉に入れてボンデングしたことを特徴とする
半導体素子のボンデング方法。1. After forming standoffs on each electrode pad of the semiconductor element, applying solder paste to the wiring pattern of the board, and aligning the semiconductor element and the board, the semiconductor element was placed in a reflow oven for bonding. Characteristic bonding method for semiconductor devices.
JP58154328A 1983-08-23 1983-08-23 Bonding method of semiconductor element Pending JPS6046039A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58154328A JPS6046039A (en) 1983-08-23 1983-08-23 Bonding method of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58154328A JPS6046039A (en) 1983-08-23 1983-08-23 Bonding method of semiconductor element

Publications (1)

Publication Number Publication Date
JPS6046039A true JPS6046039A (en) 1985-03-12

Family

ID=15581741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58154328A Pending JPS6046039A (en) 1983-08-23 1983-08-23 Bonding method of semiconductor element

Country Status (1)

Country Link
JP (1) JPS6046039A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6297341A (en) * 1985-10-23 1987-05-06 Matsushita Electric Ind Co Ltd Bonding device
EP0586243A1 (en) * 1992-09-03 1994-03-09 AT&T Corp. Method and apparatus for assembling multichip modules
JPH08172115A (en) * 1995-08-07 1996-07-02 Matsushita Electric Ind Co Ltd Bonding device and bonding

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6297341A (en) * 1985-10-23 1987-05-06 Matsushita Electric Ind Co Ltd Bonding device
EP0586243A1 (en) * 1992-09-03 1994-03-09 AT&T Corp. Method and apparatus for assembling multichip modules
US5564617A (en) * 1992-09-03 1996-10-15 Lucent Technologies Inc. Method and apparatus for assembling multichip modules
US6077725A (en) * 1992-09-03 2000-06-20 Lucent Technologies Inc Method for assembling multichip modules
JPH08172115A (en) * 1995-08-07 1996-07-02 Matsushita Electric Ind Co Ltd Bonding device and bonding

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