JPS6045450B2 - interface circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interface circuit, and more particularly, to an interface circuit that is interposed between an input/output device and a computer, in which data input and output operations are not performed simultaneously, and is an interface circuit that improves the operating speed between the two devices. The present invention relates to an improvement in an interface circuit having a data buffer register section for adjusting differences.

A conventional such interface circuit is shown in FIG.

This interface circuit 10 is a write control circuit unit that controls an input/output device 16 such as a magnetic disk device, a magnetic tape device, a character display device, etc. and a write data buffer register unit 18 for N words by a write command signal 14 from a computer 12. 20, and a read control circuit section 26 which controls the output operation of the input/output device 16 and the read data buffer register section 24 for N words in accordance with the read command signal 22 from the computer 12. 28 is an input command signal to the input/output device 16, 30 is an output command signal to the input/output device, 32 is a write request signal to the computer 12,
34 is a read request signal to the computer 12, and 36a to 34 are read request signals to the computer 12.
36n is write data from the computer 12, 38a to 38
n is input data to the input/output device 16, 40a to 40p are write control signals of the write data buffer register section 18, 42a to 42n are output data from the input/output device 16,
44a to 44n are read data to the computer 12, 46a
46p is a read control signal for the read data buffer register section 24, 48 is a write/read timing signal for writing and reading output from the computer 12, and 50 is an input/output timing signal output from the input/output device 1'6. .

In the conventional interface circuit as described above, the buffer register section and the control circuit section are configured separately for input operation and output operation, and data transfer is performed separately, so the circuit/configuration is It has the disadvantages that it is complicated, has a large number of parts, has problems in maintainability and reliability, and is also expensive. The present invention
This system was developed to eliminate the above-mentioned drawbacks of the conventional system.The number of parts required is small, and the system as a whole has high maintainability and reliability.
It is an object of the present invention to provide an interface circuit that is inexpensive and has a simple circuit configuration.

The present invention provides a computer that is interposed between an input/output device and a computer in which data input and output operations are not performed simultaneously.
In an interface circuit having a data buffer register section for adjusting the difference in operating speed between both devices, an input/output control circuit section that controls both input and output operations of the input/output device and the interface circuit using command signals from a computer. and an input selection circuit section which inputs either data from the computer or data from the input/output device to the data buffer register section by the output of the input/output control circuit section; , an output selection circuit section for outputting the memory contents of the data buffer register section to either a computer or an input/output device, so that the data buffer register section can be shared for input operation and output operation; The purpose has been achieved.

Embodiments of the present invention will be described in detail below with reference to the drawings.

In the embodiment shown in FIG. 2, the write data buffer register section and the read data buffer register section in the conventional example are replaced with a single data buffer register section 60 for N words, and similarly, the write control in the conventional example is The circuit section and the readout control circuit section are made into a single input/output control circuit section 62,
The selection signal 64 newly output from the input/output control circuit section 62 causes the write data 36a to 3 from the computer 12 to be
6n or the input/output device 16 is the output from. force data 42
An input selection circuit section 66 inputs one of a to 42n to the data buffer register section, and a selection signal 64 also output from the input/output control circuit section 62 causes the storage contents of the data buffer register section 60 to be input to the computer. 12
or! Read data 44a to 44n or input data 38a to 38 to either one of the input/output devices 16
An output selection circuit section 68 that outputs an output signal as n is provided. 70a to 70p are data buffer register sections 6;
Control signals 72a to 72n for controlling both the input operation and output operation of 0 are the data buffer register section 60.
Input signals 74a to 74n are output signals from the data buffer register section 60, and 76 is a data service request signal.

Further, the write command signal 14, read command signal 22, and write/read timing signal 48 from the computer 12 are input to the input/output control circuit section 62. Also, write data 36
a to 36n are input to the input selection circuit section 66. Further, a data service request signal 76 to the computer 12 is outputted from the input/output control circuit section 62 to the computer 12, and read data 44a to 44n are outputted from the output selection circuit section 68 to the computer. In addition, an input command L command signal 28 to the input/output device 16
and the output command signal 30 are both output from the input/output control circuit section 62 and input data 38a to 3 to the input/output device 16.
8n is output from the output selection circuit section 68. Further, the input/output tanning signal 50 from the input/output device 16 is input to the input/output control circuit section 62, and the output data 42a to 42n of the input/output device 16 is input to the input selection circuit section 66. Input signals 72a to 7 of data buffer register section 60
2n is output from the input selection circuit section 66, and output signals 74a to 74n are similarly input to the output selection circuit section 68. A selection signal 64 from the input/output control circuit section 62 is input to an input selection circuit section 66 and an output selection circuit section 68, and control signals 70a to 70p are input to the data buffer register section 60. The data buffer register section 60
can input and output data for N words at different timings using control signals 70a to 70p.

The input selection circuit section 66 selects the write data 36a to 36n and the output data 4 of the input/output device 16 according to the selection signal 64.
2a to 42n can be switched to serve as input signals 72a to 72n of the data buffer register section 60.

The output selection circuit section 68 uses the selection signal 64 to select the output signals 74a to 74n of the data buffer register section 60 as input data 38a to 38n to the input/output device 16 or read data 44a to 44n to the computer 12. You can switch and output.

The input/output control circuit section 62 sends an input command signal 2 to the input/output device 16 in response to a write command signal 14 from the computer 12.
8 and selection signal 64, or read command signal 2
2, an output command signal 30 and a selection signal 64 are issued to the input/output device 16. Also, the data buffer register section 6 is controlled by the write/read timing signal 48 from the computer 12 and the input/output timing signal 50 from the input/output device 16.
A data service request signal 76 to the computer 12 is generated depending on the control signals 70a to 70p to 0 and the storage state of the data buffer register section 60. The operation will be explained below. Let us now consider the case where write data output from the computer 12 is input to the input/output device 16. In this case, calculator 12
The write command signal 14 and write/read timing signal 48 output from the write data 36a to 36
n is input to the data buffer register section 60 via the input selection circuit section 66. Next, according to the input command signal 28 to the input/output device 16 and the input/output timing signal 50 from the input/output device 16, the storage contents of the data buffer register section 60 are changed from the data buffer register section 6 via the output selection circuit section 68. The data is read out and input to the input/output device 16 as input data 38a to 38n. If the input/output device 16 requires more data, the data service request signal 76 allows a predetermined number of data to be transferred. Contrary to the above, when reading data in the input/output device 16 to the computer 12, the read command signal 22 output from the computer 12, the output command signal 30 to the input/output device 16, and the output command signal 30 from the input/output device 16 are In response to the input/output timing signal 50, the output data 42a to 44n of the input/output device 16 are input to the data buffer register section 60 via the input selection circuit section 66. Next, data is read out from the data buffer register section 60 via the output selection circuit section 68 in response to the data service request signal 76 and the write/read timing signal 48, and is input to the predetermined data number calculator 12 as read data 44a to 44n. be done. As explained above, the present invention is interposed between a computer and an input/output device in which data input and output operations are not performed simultaneously.

In an interface circuit having a data buffer register section for adjusting the difference in operating speed between both devices, an input/output control circuit section that controls both input and output operations of the input/output device and the interface circuit using command signals from a computer. and an input selection circuit section that inputs either data from the computer or data from the input/output device to the data buffer register section by the output of the input/output control circuit section; Therefore, an output selection circuit section is provided to output the memory contents of the data buffer register section to either the computer or the input/output device, so that the data buffer register section can be shared for input operation and output operation. Since the circuit configuration of the interface circuit can be simplified and the number of parts can be significantly reduced, maintainability and reliability of the entire system are improved, and the cost is reduced. ”

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional interface circuit, and FIG. 2 is a block diagram showing the configuration of an embodiment of the interface circuit according to the present invention. 10... Interface circuit, 12...
・Calculator, 16... Input/output equipment, 36a to 36n
...Write data, 38a to 38n...
- Input data, 42a to 42n... Output data, 44a to 44n... Read data, 60...
...Data buffer register cover section, 62...
Input/output control circuit section, 64...Selection signal, 66.
...Input selection circuit section, 68...Output selection circuit section, 70a-70p...Control signal, 72a
~72n...Input signal, 74a~74n...
...output signal.

Claims (1)

[Claims] 1. In an interface circuit interposed between an input/output device and a computer in which data input and output operations are not performed at the same time, the interface circuit has a data buffer register section for adjusting the difference in operating speed between the two devices, An input/output control circuit unit that controls both the input and output operations of input/output equipment and interface circuits using command signals from the computer, and data from the computer or data from the input/output equipment by the output of the input/output control circuit unit. an input selection circuit section that inputs either one of the above to the data buffer register section, and outputs the memory contents of the data buffer register section to either the computer or the input device by the output of the input/output control circuit section. 1. An interface circuit characterized in that an output selection circuit section is provided, and the data buffer register section can be shared for input operation and output operation.