JPS6045060A - Semiconductor device - Google Patents

Abstract

PURPOSE:To simply enable the speed-up and the increase in density of a bi-polar integrated circuit by reducing unnecessary electrode wiring margins for base contact and collector contact. CONSTITUTION:By reduction of the electrode margins for the base contact 10B and the collector contact 10C by DELTAB-DELTAB' and DELTAC-DELTAC' respectively; the distances LEB between contacts is reduced to LEB, and the base parasitic resistance is reduced, leading to realization of element speed-up, and to realization of the reduction of element area is addition to the reduction of the distance LEC between contacts to LEC'. Here, the reduction of margins of the base B and the collector C enables substrate attack due to etching, as for the base contact 10B, to give no influence on the characteristics even when the attack generates more or less, because of the formation of a contact 5B and a graft base GB having a depth 3-4 times as large as that XjEB of a normal E-B junction in its neighborhood.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device that aims to simultaneously achieve higher speed and higher density of elements in a bipolar integrated circuit.

There is a strong demand for even higher speeds and higher densities for recent bipolar integrated circuits, and in order to meet these demands, efforts are being made to reduce the element area, make junctions extremely shallow, etc. In particular, the depth Xjgn of the emitter paste junction (hereinafter abbreviated as g-B junction) is formed to be extremely shallow, about 0.5 μm. In this way, extremely shallow g-
For Ibora integrated circuits with B-junctions, the manufacturing method described below is adopted from the viewpoint of reproducibility, uniformity, and prevention of deterioration of the characteristics of the B-B junction due to I-Roy spikes. The outline is shown in Fig. 1. First, as shown in Part 11 <a>, a base region B, a graft base region QB, and a thermally annealed □ film 2 are formed on an n-type silicon substrate I, and a paste is formed.

After selectively opening the emitter and collector contacts 3B, 3g, and 3C, a polysilicon film 4 is uniformly grown. Next, as shown in FIG. 1(b), a C'V D oxide film 5 is formed to cover the base contact part, and arsenic ions are implanted over the entire surface, and then this polysilicon film is used as a diffusion source. An emitter diffusion layer E and a collector contact layer C are formed by shallowly diffusing a layer on the surface.Then, the CVD oxide film 5 is removed and an Al film 6 is formed on the entire surface.
The resist film 7 is then turned as shown in FIG. 1(C). Using this resist film 7 as a mask, the Ad film 6 and the polysilicon film 4 are simultaneously dry etched to complete the wire frame arrangement. The situation is shown in FIG. 1(d).

6) (In this structure, since the polysilicon layer 4 is present between the Ad film 6 and the silicon substrate 1, it has the advantage of being able to prevent the deterioration of the 1 co-B% property due to the alloy spacing. However, the disadvantage is that Al+i% and polysilicon are dry-etched at the same time.In other words, due to the difference in the etching rate of polysilicon and A/ for the dry etching gas punch, as shown in Figure 2, side etching of polysilicon 4 is In extreme cases, the silicon substrate 1 will also be etched at the same time, and there is a risk that attack 8 will occur without seriously affecting the etching quality of the integrated circuit. As shown ((, ■゛pole arrangement f@JIB for base contact 10B, emitter contact 10g and collector contact IOC
, IIE and 11C margins ΔB, Δ1 and Δ
C is designed to be 2 μm or more in consideration of mask alignment misalignment and the above-mentioned etch position. Straight wiring spacing ΔL
1) The minimum thickness that can be stably and productively achieved using etching technology and dry etching technology is 2 μm. It pole margin ΔB,
△p2. The minimum distance LF, B between the emitter contact and the base contact and the minimum distance LF, C between the emitter contact and the collector contact are determined, and at the same time, the minimum distance LF, C between the emitter contact and the collector contact is determined. Minimum 1i
Fi Maki is also determined. Therefore, unless there is a combination of photolithography technology and dry etching technology, high performance 11R elements cannot be expected.

The present invention has been developed by focusing on this point. In a bi-bone integrated circuit, the margin of polarization for wiring for one tact of emitter is larger than the margin of electrode for wiring for base contact and collector contact. It concerns semiconductor devices characterized by their large size.
Current photolithography and dry etching technologies can simultaneously increase the speed and density of bipolar integrated circuits; I! The purpose is to provide a semiconductor device that can

Next, the present invention will be explained in detail with reference to examples. Figure 3 (b
) is an embodiment of the present invention based on the conventional example shown in FIG. 3(a). That is, as shown in FIG. 3(b), the margins of the electrodes for the base contact and the collector contact are reduced to ΔB=ΔB/, 80-80' compared to FIG. By reducing the LEB to an LED', the base parasitic resistance is reduced and the device speed is increased, and by reducing the 5LEC to an LEC', the device area is also reduced. here,
By reducing the margins of the base and collector parts, the above-mentioned substrate attack due to etching becomes a problem, but when we investigated this effect, we found that the first
As shown in the figure, there is usually g-B at the contact and its vicinity.
The graft base is 3 to 4 times as deep as the depth of the joint (
JB was formed, and it was found that even if some substrate attack occurred, the characteristics would not be affected, and there were no problems with the collector contact. That is,
For the base contact and the collector contact, it is not necessary to consider the substrate attack due to the side etching of the polysilicon, and it is only necessary to consider misalignment.

As explained above, according to the present invention, it is possible to easily reduce unnecessary electrode wiring margins for the base contact and collector contact, and to increase the speed and increase the tb of the Ibora integrated circuit. Since they can be realized simultaneously, the effects of the present invention are extremely large.

[Brief explanation of the drawing]

Fig. 1 ta+~(dl is a cross-sectional view showing an example of the conventional manufacturing method of a bipolar integrated circuit 1i circuit, Fig. 2 is the same as Fig. 1 (d)
A cross-sectional view showing an enlarged portion of the emitter electrode in
FIG. 3(a) is a plan view of a conventional device, and FIG. 3(b) is a plan view of a device showing an embodiment of the present invention. 1...Silicon substrate, 2...Thermal oxide film, 313. 3E, 3C... Electrode contact, 4.
...Polysilicon, 5...CVD oxide film, 6
......Al film, 7...Resist film, 8.
...Attack, 9.9'...Element area%
10B, loE, 1oC...Contact, + +
13. l J J 11c, ] IB', I IC'・
=-'UftJe, line, B...Base E...
...Emitter C...Collector, GB...
...f 9-7 topace, ΔB, ΔB, ΔC1
ΔB', ΔC/... Electrode wiring margin for contact, ΔL-..., wiring spacing, "F, B l
“EB” + LEc * “EC”””” Distance between contacts. Agent: Susumu Uchihara, Patent Attorney, Figure 1, Figure 2

Claims (1)

[Claims] 1. A semiconductor device in a bipolar integrated circuit, wherein a margin of a wiring electrode with respect to an emitter contact is larger than a margin of the wiring electrode with respect to a pace contact and a collector contact.