JPS6045036A - Substrate structure of semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To produce flat and highly integrated separation region between elements by a method wherein a deep groove for separating elements filled with dielectric and filler as well as a field oxide film are selfmatchingly formed. CONSTITUTION:A thick field oxide region 25 is formed adjoining element region selectively formed on a silicon substrate 11 while a separation region between elements directly coming into contact with the field oxide region 25 is provided between the element region and the field oxide region 25. Furthermore, the separation region between elements is composed of a relatively narrow and deep groove 11a formed on the silicon substrate 11, an oxide silicon insulating film 21 formed along the inner wall of this groove 11a, a nitride silicon insulating film 22 arranged on the film 21 and filler 24 filling the recession formed between the inside, the nitride silicon insulating film 22 and the field oxide film 25. The resultant element region of the silicon substrate 11, the field oxide region 25 and the separation region between elements may be formed into almost flat surface.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a substrate structure of an integrated circuit semiconductor device in which a large number of elements are incorporated on the same substrate, and a manufacturing method thereof.

[Prior art]

Conventionally, as a method for separating elements in this type of semiconductor device, a selective oxidation method in which the periphery of an element is selectively thermally oxidized has been put into practical use. Various methods have also been devised to form a groove around the element and fill it with dielectric material.

Among these methods, in the case of the selective oxidation method, for example, in the case of a bipolar process, it is necessary to completely separate the epitaxial layer with an oxide film, and the redistribution of impurities deteriorates the device performance due to long thermal fermentation.

Additionally, bird's beaks and bird's heads are formed during selective oxidation, which hinders high integration of integrated circuits.

On the other hand, with the method of forming a trench and filling it with dielectric material, it is generally possible to only form an isolation region with a certain narrow width, and it is not possible to obtain a structure in which a thick field oxide region for wiring is directly in contact with an isolation trench. It wasn't.

Even if a thick field oxide region adjacent to the isolation trench were formed as proposed in the past, a new photolithography process would be required, which would complicate the process, as well as problems with mask alignment. Taking margin into consideration, when forming a field oxidation region, it is impossible to form a field oxidation region with no bird's beak or bird's head by directly pouring liquid into the groove, so a fault occurs between the trench and the field oxidation region. There is a drawback that a substrate with a flat surface cannot be realized. Furthermore, since some bird's beaks and the like remain, it is difficult to improve the degree of integration. Furthermore, with conventional groove separation technology, the groove pattern is formed using ordinary exposure technology, making it impossible to achieve groove widths that are below the limits of exposure technology, which also limits the ability to improve the degree of integration. . Further, when the groove width is widened by conventional groove separation, there are also drawbacks such as the grooves not being completely filled with the dielectric material and the surface not being flat.

[Object and structure of the invention]

The present invention has been made in view of the above circumstances, and an object thereof is to provide a substrate structure for a semiconductor device that is flat as a whole and that allows an integrated circuit with a high degree of integration, and a manufacturing process in which such a substrate structure is simplified. An object of the present invention is to provide a method for manufacturing a substrate structure of a semiconductor device.

To achieve this purpose, the substrate structure of the semiconductor device according to the present invention includes a field oxide region between an element region selectively formed on a silicon substrate and an adjacent thick field oxide region. Deep grooves for isolation between elements are formed so as to be in direct contact with each other, and these are filled with a silicon oxide insulating film, a silicon nitride insulating film, and a filler to form a flat surface as a whole.

In addition, in order to obtain such a force structure, the method for manufacturing a substrate structure of a semiconductor device according to the present invention uses anisotropic etching for a pattern region covering an element region, thereby allowing self-alignment between elements. After forming a deep trench for isolation and sequentially forming a silicon oxide insulating film and a silicon nitride insulating film on the inner wall of this trench, the remaining recess is filled with a filler material, and one silicon substrate surface facing the trench is Before oxidizing to form a field oxide film, it is recommended that the surface of the silicon substrate in the field oxidation region be etched to remove a portion approximately % thicker than the field oxide film to be formed. In other words, the surface is made flat as a whole. Hereinafter, the present invention will be explained in detail using Examples.

〔Example〕

FIGS. 1(a) to 1(g) are process cross-sectional views showing an example of a method for manufacturing a substrate structure of a semiconductor device according to the present invention.

In the figure, first, a layer with a thickness of, for example, 50 mm is placed on the silicon substrate 11.
A thermally oxidized silicon (StO) film 12 with a thickness of about 150 nm is formed on this 5IOa film 12 by a CVN method or the like.
A silicon nitride (SilIN4) film 13 of m thickness is formed, and then a silicon nitride (SilIN4) film 13 of about 6 m thickness is formed on this 5S8N film 13 by the method of
A silicon oxide (stolI) film 14 with a thickness of 0.00 nm is formed.

Here, a photoresist 15 having a thickness of, for example, 1 μm is formed in a predetermined pattern on this 5102 film 14, and using this as a mask, for example, reactive ion etching using CI (F8 gas) is performed. S
The entire iO2 film 12 is removed to expose the surface of the silicon substrate 110. As a result, a desired element isolation pattern can be formed (FIG. 1(a)).

For example, a silicon nitride (SigN4) film 16 with a thickness of 500 nm is formed by, for example, a low pressure CVD method (see FIG.
b)).

Next, the Si8N4 film 16 is etched by the thickness of the film by reactive ion etching using, for example, CHF5 gas until the silicon substrate 1 is exposed. Since reactive ion etching is used, the flat portion of the SigN film 16 is removed, leaving a silicon nitride (8111N+) region 1T only in the stepped portion of the element isolation pattern. At this time, 81
8N, the width remaining on the silicon substrate 11 in the region 1γ is 5iB.
The thickness is approximately equal to the thickness of the N4 film 16, for example, about 500 nm in this case. Actually, the thickness of the 818N4 film 16 is changed to form a 518N4 region 17 having a width in the range of 100 to 500 nm. Silicon substrate 1 exposed in this state
For example, by thermally oxidizing 1, silicon oxide with a thickness of 30 Qnm (
Sing) film 1B is formed.

This S i O 2 film 18 serves as a mask material layer when etching the silicon substrate 1 to form grooves later (FIG. 1(C)).

Next, after removing the 5iaN4 region 17 by wet etching with phosphoric acid or the like, the silicon substrate 11 is etched by about 300 nm by reactive ion etching using, for example, SIC gas.
A groove 11a is formed by μm etching (Fig. 1(d)).
). The depth of this groove 11& is determined in relation to the inter-element withstand voltage required for isolation between the elements in that portion. FIG. 2 shows an example of that relationship. The silicon substrate used to measure this characteristic was a (111) P- silicon substrate whose surface was doped with N+ ions, and an N layer was epitaxially grown thereon.

After the formation of $11a, for example, dose ii is placed near the bottom of $11a.
1 x 1018CTn-", a channel cut region 19 is formed by a bow ion implantation with an acceleration voltage of 30 KeV,
After removing the 5IO1I film 1T by etching, the exposed silicon substrate 11 is removed by an amount equivalent to about the thickness of the field oxide film to be formed after being subjected to reactive ion etching using, for example, f3lC1h gas.

After that, the exposed silicon substrate 11 and the groove 11a are
The inner surface of the silicon oxide (810,) film 20 and 21 with a thickness of 50 nm, for example, and the reduced pressure CV
For example, 150 nm thick silicon nitride (81
8N4) After forming the film 22 on the entire surface, a filling material 23 made of an insulating material, such as a silicon oxide film, is applied to fill the recess 11b formed inside the Sl, N4 film 22 by, for example, a depressurization method. (Fig. 1(e))
).

Next, the filler 23 is subjected to anisotropic reactive ion etching to remove the flat portion, leaving only the portion of the filler 24 where the recess 11b is filled. At this time, the surface of the filler 24 forms a rounded slope from the higher left side, the lower edge of the Si8N4 film 22 in the element formation region to the lower right side, and the edge of the 818N4 film 22 in the field oxidation region.

Next, the exposed 818N4 film 22 is removed by reactive ion etching, and the exposed 5102 film 20 is further etched until the silicon substrate 11 is exposed, and the 5ins film 14 is removed (FIG. 1(f)).

Next, the exposed silicon substrate 11 is heated at 900° C., 8
Atmospheric pressure, pyroge for 100 minutes
nlc) Selective oxidation is performed to form a field oxide film 25 with a thickness of about 1 μm which will become a wiring region. The field oxide film 25 thus formed is formed to approximately the same height as the upper surface of the 5I02 film 12 covering the silicon substrate 11, and the entire substrate surface is approximately flat. However, when forming this field oxide film 25, 5
The t8N4 membrane 22 is exposed and the filler material 24
Since the surface of the field oxide film 25 forms a curved surface that descends toward the exposed portion, the field oxide film 25 cannot completely cover the upper part of the filler 24, and a slight recess 11c is formed between the filler 24 and the field oxide film 25. It often remains in between. For this reason,
In order to fill these four parts 11e, a supplementary filling material made of a CVD silicon oxide film similar to the filling material 24 is formed on the entire surface, and then this filling material is etched onto the surface of the field oxide film 25 by anisotropic reactive ion etching. is removed until it is exposed, leaving only the filler 26 in the part where the recess 11e is buried. Finally, the 818N4 film 13 exposed on the element formation region is removed by etching with hot phosphoric acid.
A substrate structure is obtained in which the trench isolation portions are in direct contact with the thick field oxide film 25, and the trench isolation portions, the field oxide film 25, and the upper surfaces of the device regions are generally flat as a whole (FIG. 10)). After this, the SiO2 film 1 in the element region
2 is removed and a desired device structure is formed there.

In such a substrate structure, the field oxide film 25 and the trench isolation region are in direct contact with each other, and the top surface is flat, so the width required for isolation is narrow, making it suitable for high integration and making wiring easier. It has the advantage of being easy. Furthermore, since the field oxide film 25 and the trench isolation region are separated halfway by the short Sll]N4 film 22 that does not reach the substrate surface, the stress caused by the thick field oxide film 25 is moderately relaxed. Defects may occur in the element region. Therefore, characteristics such as hfe are less likely to deteriorate.

In the embodiment described above, when forming the SIO film 18, the thick 5IBN4 region 11 was used as a mask at 900°C.
If wet oxidation is performed to form an 8102 film with a thickness of 0.75 μm or more, crystal defects may occur in the silicon substrate 11. In order to avoid this, a method as shown in FIG. 3 may be used. That is, after obtaining the structure shown in FIG. 1(,) in the same manner as described above, the resist 15 is removed, and a silicon nitride (SI3N4) film with a thickness of 50 nm or less is formed on the entire surface by, for example, the reduced pressure C method. After forming 27,
On top of that, for example, a thickness of about 500
Form a polysilicon film 28 with a thickness of nm (FIG. 3(a))
. If this polysilicon film 28 and 5iBN4 film 27 are used as a substitute for the thick silicon nitride region 17, the occurrence of crystal defects in the silicon substrate 11 can be prevented since the only silicon nitride film is the thin 5iBN film 27. .

In this case, the polysilicon film 28 can be replaced with another material that similarly has excellent step coverage. For example, it is possible to use a CVD silicon oxide film, a sputtered At film or other metal film, an At oxide film, a germanium oxide film, a polymer material film such as photoresist, or the like.

Therefore, the polysilicon film 28 is removed by an amount equivalent to the film thickness by reactive ion etching to form a polysilicon region 29 (FIG. 3(b)).

Next, using this polysilicon region 29 as a mask, 5IB
The N4 film 27 is etched to expose the silicon substrate 11. Thereafter, the polysilicon region 29 is removed by etching, and the silicon substrate 11 is thermally oxidized using the remaining 518N4 film 30 in the stepped portion as a mask to thermally oxidize the silicon oxide (81N4).
011) Form a film 31 (FIG. 3(C)). In this case, a 5 inch film 31 may be formed while leaving the polysilicon region 29, and then the polysilicon region 29 may be removed. Further, the 5t3N4 film 30 may be used as long as it serves as a selective oxidation mask; for example, if the 5i02 film 31 is formed by plasma oxidation or anodic oxidation, an alumina film or the like may be used instead of the 5i8N film 30. After this,
The S'8N4 film 30 is removed and the same steps as shown in FIG. 1(d) and subsequent steps are performed.

In the embodiment described above, a multilayer structure may be used in which a silicon oxide (STO2) film is further interposed between the 5i8N film 27 and the polysilicon film 28. This is shown in Figure 4. That is, FIG. 4 shows 818N film 2 with a thickness of about 30 nm.
810.7 with a thickness of 70 nm, for example, and the polysilicon film 28 with a thickness of about 500 nm. This is an example in which a membrane 32 is added.

Further, the step of etching the silicon substrate 11 in the field oxidation region shown in FIG. 1(,) may be performed before forming the trench 11a or immediately after obtaining the structure shown in FIG. 1(,). can. An example is shown in FIG. That is, as shown in FIG. 1(,), an 810g film, a 2.5IBN4 film 13, and a 5tOQ film 14 formed on a silicon substrate 11 are etched by reactive ion etching using CF4 gas using a photoresist 15 as a mask. After etching, the exposed silicon substrate 11 is subjected to reactive ion etching using STCT4 gas to remove about % of the field oxide film thickness (FIG. 5(IL)).

Thereafter, after removing the photoresist 15, the 5iRN4 film 33.5IO1I film 34 and polysilicon film are formed by, for example, a reduced pressure method (FIG. 5(b)), similarly to the example shown in FIG.

In this state, the polysilicon film 35 was removed by reactive ion etching using 5iC44, leaving only the stepped portion, and then the exposed 8102 film 34 was removed using hydrofluoric acid using the remaining polysilicon region as a mask. After that, the polysilicon region was removed, and the remaining sto film 34 was used as a mask to remove the TE5i8N4 film 33 with hot phosphoric acid, and then the 5I8N4 film 33 was removed using hot phosphoric acid.
Remove the o8 film 34 with hydrofluoric acid and apply 5iB only to the step part.
N, to form a film 36. (7) 818N, the width of the membrane 36 is 818N, the width of the membrane 33.810! It is approximately equal to the total thickness of the film 34 and the polysilicon film 35, and is approximately 700 mm here.
nm. Next, when thermal oxidation is performed using this 818N4 film 36 as a mask, a silicon oxide (S102) film 3T having a thickness of, for example, 300 nm is formed (FIG. 5(C)).
.

After removing the film 3B by wet etching with phosphoric acid or the like, the silicon substrate 11 is etched by about 3 μm by reactive ion etching to form a groove 11m, and boron ions are implanted at the bottom to form a channel cut region 3.
B is formed (Fig. 5(d)).

After removing the 8%02 film 37 by etching, thermally oxidized silicon (SIO) films 39 and 40 having a thickness of, for example, about 50 nm and a low pressure CVD silicon oxide (Si3N) film 41 having a thickness of, for example, 150 nm are formed. Furthermore, a filling moon 42 made of silicon oxide and having a thickness of 400 nm, for example, is formed (FIG. 5 (6)).

Fillers 42 and 5 are then etched by reactive ion etching.
A portion equivalent to the thickness of the lsN4 film 41 is removed, leaving only the filler 43, and then StO! The entire film 39 is removed by etching 810. Remove the film 14 (fifth
Figure (f)).

Next, the exposed silicon substrate 11 is selectively oxidized using a pyrogenic method to form a field oxide film 44, the remaining recesses are filled with a supplementary filler 45, and finally the Si, N, film 1
3 is removed with hot phosphoric acid (Figure 5(g)).

If it is possible to form even finer patterns, in addition to forming a thick field oxide film of approximately 2 μm or more and deep trenches as described above, shallow trenches of approximately 1 μm as shown in FIG. Separate structures are possible. This will be explained next.

First, thermally oxidized silicon (Sin) is deposited on the silicon substrate 46.
g) Membrane 47. A silicon nitride (SigN+) film 48 and a silicon oxide (S102) film 49 are formed in this order, and then etching is performed using a photoresist (not shown) having a predetermined pattern placed thereon as a mask to form a silicon substrate 46. expose the surface. This forms a desired element isolation pattern, but in this case,
5iOII is applied to the area where shallow grooves are to be formed in the element formation region.
A through hole 50 passing through the film 49.5iBN4 film 48 and StO film 47 is formed at the same time. At this time, 510
1! Membrane 47, S i 8N4 membrane 48 and 5102 membrane 4
The thickness fI of 9 needs to be larger than the width of the through hole 50, that is, the width W of the shallow groove to be formed. Next, a silicon nitride (SisN+) film 51 and a polysilicon film 52 are deposited on the entire surface (FIG. 6(a)).
.

Next, reactive ion etching is performed on the polysilicon film 52 to remove the polysilicon region 53 at the stepped portion and the through hole 5.
Only the buried polysilicon region 54 within 0 is left (FIG. 5)).

Next, using the polysilicon regions 53 and 54 as a mask, 5iB
Then, the film 51 is removed by etching to expose the surface of the silicon substrate 46 (FIG. 6(C)).

Next, wet etching is performed to remove the polysilicon region 53 by an amount equivalent to the thickness of the polysilicon film 52, leaving the polysilicon region 55 in the through hole 5o (FIG. 6(d)).

Next, the exposed silicon substrate 46 is oxidized, and at the same time, the polysilicon in the through hole 50 is oxidized to thermally oxidize silicon (
A StO2) film 56 and a polysilicon oxide film 57 are formed. Thereafter, deep grooves 46a for separating multiple elements are formed by reactive ion etching (FIG. 6(e)).

Next, the 5i8N film 51, the polysilicon oxide film 57, and the Sto film 49 on the surface where the shallow groove is to be formed are removed by etching. Since the 5tOPI film 49 is formed thicker than the other films, a portion thereof remains without being removed. Thereafter, after etching the shallow groove 58 and the silicon substrate 46 in the field oxidation region at the same time, a channel cut region 59 is formed by ion implantation (FIG. 6(f)).
.

Hereinafter, a silicon oxide (STO2) film 60. Silicon nitride (
818N4) After arranging the film 61 and a filling material 62 made of silicon oxide and forming a thick field oxide film 63, the recess is filled with a supplementary filling material 64, and finally the 518N film 48 on the element region is removed. By this, Figure 1 (
A structure similar to that shown in (g) can be formed (Fig. 6 (g)
).

FIG. 7 shows a structure in which a bipolar transistor is formed on a substrate having an isolation region completed in this way. Arsenic was diffused over the entire surface to a surface concentration of 1 x 10 cm to form an n+ layer 67 that would serve as a collector buried layer, and an n-type silicon layer 68 with a thickness of about 1 μm was epitaxially grown on it. It is something. Since each element is later separated by a trench isolation region, n
+The buried layer does not need to be formed independently using a mask having separate patterns in advance, and may be formed over the entire surface in this way. Further, 69 is a p+ channel cut region, 7G is a field oxide film with a thickness of approximately 1 μm, 71 is a silicon oxide (StO,) film formed on the inner wall of the deep trench and shallow trench for element isolation, and 72 is this 5 lot film. A silicon nitride (8111N4) film formed on T1, 73 is a filler, 74 is a supplementary filler, T5 is an n+ diffusion layer, 76 is a p+ diffusion layer, 77 to T9 are a base, an emitter,
Each electrode of the collector.

This structure is also applicable to 80I (silicon on insulator) substrates. The structure in that case is shown in FIG. In the figure, 80 is an insulating substrate. Instead of an insulating substrate, a buried insulating layer formed in a silicon substrate may be used.

Although FIGS. 7 and 8 show the case where a bipolar transistor is formed in the element region, it is of course possible to form other elements such as an MDS transistor or a CMOS transistor.

In the substrate structure as described above, the inter-element reverse breakdown voltage is approximately 18V, and for example, when a bipolar LSI is fabricated in the element region, this value is approximately three times or more compared to the operating voltage of 5V, so a sufficient breakdown voltage is required. It was confirmed that this can be achieved. Note that this breakdown voltage can be further increased by increasing the depth of the groove as shown in FIG.

Furthermore, when crystal defects in the element region were examined by dilt etching, it was confirmed that no crystal defects that would cause deterioration of element characteristics were generated in the element region.

In the embodiments described above, for example, Q■
Although the case where an insulating material such as a silicon oxide film is used has been described, the present invention is not limited thereto, and the filling material C may be an insulating material such as polysilicon, a semi-insulating material, a quaternary electric material, etc. You can also use Here,
As the semi-insulating material, for example, silicon oxynitride (Styo0yN2), oxygen-doped polysilicon, silicon nitride (St,,N,), etc. are used, and as the conductive side diagonal, Mo, W, Pt are used. High melting point metals such as When using conductive fillers such as polysilicon, semi-insulating materials, or conductive materials, it is possible to reduce charges generated in these areas due to radiation irradiation, creating elements with strong environmental resistance. Can be manufactured. In this case, the filler is approximately 100 μm thick so that the charge accumulated in the silicon nitride film in the deep trench can be discharged.
It is desirable to have a resistivity of σ or less, and the production process of the above-mentioned semi-insulating material is adjusted by a known method so that it has such a resistivity value.

〔Effect of the invention〕

As explained above, according to the present invention, since the deep groove for element isolation filled with the dielectric material and the filler material and the thick field oxide film are formed in a self-aligned manner, the thick silicon oxide film Bird's beaks and bird's heads hardly occur at the ends, and a flat shape in which the thick field oxide film is in direct contact with the deep trench can be created, making it possible to easily obtain an element isolation structure with excellent high integration.

In addition, the width of the deep groove is not limited by the limits of exposure technology and can be controlled by the thickness of the film subjected to anisotropic etching, making it suitable for miniaturization. Since shallow trenches and thick field oxide films in the device region can be formed in a self-aligned manner, a structure can be obtained that eliminates the conventional problems of parasitic capacitance due to field mismatch, parasitic MO8, and surface steps (bird's head). be able to. Therefore, higher speed, higher integration, and higher yield of LSI can be achieved.

Furthermore, according to the present invention, a trench with a fine width, a thick field oxide film, and a shallow trench are formed in one pattern around the element region, and the surface is flat and there is no difference in pattern conversion. l[1 separation tf4 structure can be formed. In addition, the buried layer pattern is uncomfortable for bipolar, CMO
The high speed and low power consumption of devices such as 8 and Bt-Mos can be achieved.

[Brief explanation of drawings]

1(a) to 0) are process cross-sectional views showing one embodiment of the present invention, FIG. 2 is a diagram showing the relationship between the depth of the groove for isolation between elements and the withstand voltage between elements, and FIG. ) to (C) are process cross-sectional views showing other embodiments of the present invention, FIG. 4 is a cross-sectional view showing still other embodiments of the present invention, and FIGS. Process sectional views showing other embodiments, FIGS. 6(A) to (2)
)) is a process cross-sectional view showing still another embodiment of the present invention, and FIGS. 7 and 8 are cross-sectional views each showing an example of a semiconductor device formed using the substrate structure of one embodiment of the present invention. . 11.46.65--- ・Silicon substrate, 11a, 4
6a...deep groove, 11b, 11c...recess, 1
2, 14° 18.20, 21, 31, 39.40, 4
7.49,56,57°60,71...Silicon oxide film, 13,22,27°37.41,48,51
,61.72...Silicon nitride film, 17,30,
36,53.54...silicon nitride region, 23,
24, 42, 43, 62.73 ... filler (first
filling material), 25, 44.63.70... field oxide film, 26, 45, 64.74... filling material (second filling material), 50... through hole, 58 ...Shallow groove, 6T...n+ layer (silicon substrate), 68...
・N-type silicon layer (silicon substrate). Agent Masaki Yamakawa Continuation of Figure 7, Figure 8, Page 1 ■Int, CI,' Identification code Internal reference number // H
01L 29/72 @ Inventor Nobuyoshi Awaya Atsugi Telecommunications Research, Nippon Telegraph and Telephone Public Corporation, 183 Hata Estate, Ono, Atsugi City

Claims (6)

[Claims] (1) A device region selectively formed on a silicon substrate, a thick field oxide region formed adjacent to this device region, and a field oxide region formed between these device regions and the field oxide region The device isolation region includes a relatively narrow and deep trench formed in the silicon substrate, a silicon oxide insulating film formed along the inner wall of the trench, and a silicon oxide insulating film formed along the inner wall of the trench. It is composed of a silicon nitride insulating film disposed on a silicon oxide insulating film, and a filling layer that fills the recess formed inside the silicon nitride insulating film and between the silicon nitride insulating film and the field oxide film. 1. A substrate structure for a semiconductor device, wherein surface lines of an element region, a field oxidation region, and an element isolation region on a silicon substrate are formed substantially flat. (2) An element region selectively formed on a silicon substrate, a field oxide region formed adjacent to the element region, and a field oxide region formed between these element regions and the field oxide region. The device isolation region includes a relatively narrow and deep trench formed in the silicon substrate, a silicon oxide insulating film formed along the inner wall of the trench, and a silicon oxide insulating film formed along the inner wall of the trench. Consisting of a silicon nitride insulating film disposed on a silicon oxide film, and a filler filling the four parts formed inside the silicon nitride insulating film and between the silicon nitride insulating film and the field oxide film, The device region has a shallow groove filled with a silicon oxide insulating film formed along the inner wall and a silicon nitride insulating film disposed on the silicon oxide insulating film, and the device region on the silicon substrate A substrate structure for a semiconductor device, characterized in that the surfaces of the field oxidation region and the element isolation region are formed substantially flat. (3) Using anisotropic etching and a step of forming a multi-MM pattern region consisting of layers each having different etching characteristics on the silicon substrate in the element formation region,
forming a thin film region of a predetermined width on the surface of the silicon substrate in a self-aligned manner adjacent to the pattern region; The process includes a step of forming an etching mask material layer with different etching characteristics, a step of etching the silicon substrate exposed by removing the thin film region to form a deep and narrow groove for isolation between elements, and A step of etching the surface of one silicon substrate facing the deep trench to remove a portion approximately % thicker than the field oxide film to be formed, and etching a silicon oxide insulating film and a nitride film along the inner wall of the deep trench. After arranging the silicon insulating film 11, there is a step of filling the formed recess with a filler, and a field oxidation process is performed by oxidizing the surface of the silicon substrate 9, which has been removed to a thickness of approximately H of the field oxide film to be formed. 1. A method for manufacturing a substrate structure of a semiconductor device, comprising the step of forming a film, and forming an element isolation region and a field oxidation region almost flat with respect to an element region. (4) A process of forming a multilayered pattern area consisting of layers each having different etching characteristics on the silicon substrate in the element formation area, and etching the surface of the silicon substrate using this pattern area as a mask to form a field. A thin film region of a predetermined width is formed in a self-aligned manner adjacent to the pattern region by removing the oxide film to a thickness of about 10% of the oxide film and using anisotropic etching. a step of forming on the surface of the
A step of forming an etching mask side layer having etching characteristics different from that of the silicon substrate on the surface of the silicon substrate exposed other than the thin film region and the pattern region, and etching the silicon substrate exposed by removing the thin film region. After that, a silicon oxide insulating film and a silicon nitride insulating film are sequentially arranged along the inner wall of this deep trench, and then the four parts to be formed are filled with a filling material. and a step of forming a field oxide film by oxidizing the surface of the silicon substrate which has been removed to a thickness of approximately % of the formed flat field oxide film, and forming a field oxide film in the element isolation region and the field oxide film. A method for manufacturing a substrate structure of a semiconductor device, characterized in that an oxidized region is formed substantially flat. (5) A step of forming a pattern region of a multilayer structure consisting of layers each having different etching characteristics on the silicon substrate in the element formation region, and using anisotropic etching.
a step of forming a thin film region of a predetermined width on the surface of the silicon substrate in a self-aligned manner adjacent to the pattern region; A step of forming an etching mask material layer with different etching characteristics, a step of etching the silicon substrate exposed by removing the thin film region to form a deep and narrow groove for isolation between elements, A field to be formed by etching the surface of one silicon substrate facing the trench - a step of removing the oxide film to a thickness of approximately %, and a silicon oxide insulating film and a nitride film along the inner wall of the deep trench. After sequentially arranging the silicon insulating films, filling the recesses formed inside the silicon nitride substrate with a first filler, and removing the silicon substrate to a thickness of about % of the field oxide film to be formed. A step of oxidizing the surface of the field oxide film to form a field oxide film, and a step of oxidizing the recess formed between the field oxide film and the silicon nitride insulating film disposed in the deep trench and the first filler with a second filler. 1. A method of manufacturing a substrate structure of a semiconductor device, comprising: filling an element isolation region and a field oxidation region substantially flat with respect to an element region. (6) The process of forming a multilayer structure pattern area consisting of layers each having different etching characteristics, each having a through hole in a part, on the silicon substrate in the element formation area, and using anisotropic etching. forming a thin film region of a predetermined width on the surface of the silicon substrate in a self-aligned manner adjacent to the pattern region; a step of forming an etching mask material layer with different etching characteristics; a step of etching the silicon substrate exposed by removing the thin film region to form a deep and narrow groove for isolation between elements; A step of etching the surface of one silicon substrate facing the hole portion and the deep groove to remove the field oxide film to be formed to a thickness of about H, and etching silicon oxide along the inner wall of the deep groove. After sequentially arranging the insulating film and the silicon nitride insulating film, filling the formed recess with a filler;
forming a field oxide film by oxidizing the surface of the silicon substrate which has been removed to a thickness of about H of the field oxide film formed above, and forming an element isolation region for an element region provided with a shallow trench. and a method for manufacturing a substrate structure of a semiconductor device, characterized in that a field oxidation region is formed substantially flat.