JPS6043935A - Signal synchronous converter - Google Patents

Abstract

PURPOSE:To convert accurately a low frequency asynchronous input data string into a high speed data string by applying quickly phase locking in converting the low frequency asynchronous input data string into the high speed synchronous data string. CONSTITUTION:A shift register 1 receiving an input data Si and a shift register 2 receiving an input frame pulse SFi generated corresponding to the heat bit of the frame of the input data Si are provided. Further, an AND gate 5 and a delay stage number detecting circuit 6 are provided, an output of the shift register 2 is applied to a selector 4 and also to one input terminal of each of AND gates 5. A delay deciding pulse signal from a pulse generating circuit 8 is applied to the other input terminal of each and the output of the register 2 and a phase locked position is detected by the delay number of stage detecting circuit 6. The detected output is applied to selectors 3, 4. Further, an elastic store memory 7 and a pulse generating circuit 8 are provided.

Description

[Detailed Description of the Invention] Technical Field of the Invention The present invention relates to a multiplex data communication device, and more particularly, to multiplexing mutually asynchronous input data strings from a plurality of terminals such as telephones and facsimile machines. The present invention relates to a signal conversion device that converts a high-frequency data string into a high-frequency data sequence synchronized with an output clock.

Background of the technology, conventional technology, and problems A low-frequency disotal data string that is asynchronous to each other is converted into a high-frequency disotal data string, and multiple signals thus converted are multiplexed to perform data communication. A multiplex data communication device is already known. In this case, a low-frequency distal data stream is input in a predetermined frame, but is synchronized with the high-speed side to be converted. It is not possible to perform high-speed conversion with accurate phase synchronization.

For this reason, in the conventional method, when converting low-speed asynchronous input data into a high-speed synchronous data string, human data is selected one stage at a time using a multi-stage shift register until the phase matches the high-speed side. I was trying to get phase synchronization. However, with this method, depending on the transmission timing of asynchronous input data and the timing on the high-speed side, it takes up to a maximum of time equivalent to the number of frames for the number of stages of the shift register to properly establish phase synchronization. , there is a problem that phase synchronization lacks speed.

Purpose of the Invention In view of the above-mentioned problems, the present invention provides that when converting a low-frequency asynchronous input data string into a high-speed synchronous data string in a multiplex data communication device, phase synchronization is first quickly established, and based on this interphase loop. The object of the present invention is to provide a signal synchronization/conversion device which accurately converts data into a high-speed data stream.

Structure of the Invention In the present invention, a data string of a predetermined frame length is sequentially received and a signal string responsive to a predetermined clock is output.
- a first register that receives a frame signal indicating the beginning of each frame of the input data string, and a second register that outputs a pulse train responsive to the predetermined clock; a pulse generation circuit that generates a timing signal indicating the beginning; a phase synchronization detection circuit that compares the timing signal with the output pulse train of the second register to detect a phase synchronization position; There is provided a signal synchronization/conversion device completely equipped with storage means for sequentially storing the output pulse train of the register and outputting the stored data in response to a clock on the conversion side based on a signal from the pulse generation circuit. Ru.

Embodiment of the Invention An embodiment of the invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a circuit diagram of a signal synchronization/f conversion pupil based on the present invention. In FIG. Shift register 2 receives all input frame pulses SFi generated corresponding to bits.
The input clock signal CLKi is manually input to the shift registers 1 and 2, and the signals input to the respective shift registers are shifted by this clock signal, resulting in a narrow shift.1. For example, it is output as a parallel signal that is delayed or delayed by M. In this example, the frame length (γ
The output signals S1 and S2 of shift registers 1 and 2 are 6 bits, and the output signals S1 and S2 of shift registers 1 and 2 are 6 bits. Figure 2 (a) ω) (C
).

Therefore, the output signal S2 of the shift register 2 is ω)~
The signals are represented as signals 821 to S26 shown in (i).

, the input capter S1 synchronizes with the input frame signal SFi and frames within a range of 6 bits (B).

(C), (1)) are input (Fig. 2 (C)), but the data in the valley frame is a logic "0" or [1].
"1, 11↓, and FIG. 2 (C) shows the case where all logic "1" data is input so that the timing is clear.

The box further includes a six-stick AND gate 5 and a delay stage number detection circuit 6, and the signals S21 to 826 are applied to the selector 4 and to one input terminal of each of the AND gates 5. The opening force is n. Each A N D key
A delay determination pulse signal SI) from a pulse generation circuit 8, which will be described later, is applied to the other input terminal of the signal 821.
When the timings of one of the signals SD and the signal SD coincide with each other in S26, the delay stage number detection circuit 6 detects the matched stage number, that is, the position where the phases are synchronized. This operation will be described later. The phase synchronized position signal S6 detected by the detection circuit 6 is applied to the selectors 3 and 4 of the device.

The output signal S] of the shift register is applied to the selector 3, and the output signal S2 of the shift register 2 is applied to the selector 4. The output signals of selectors 3 and 4 are applied to elastic store memory 7. These operations will be described later.

The device also includes an elastic store memory 7 and a pulse generation circuit 8. The timing chart of the elastane ink store memory 7 is shown in FIG.
Data input to the input terminal Din (Figure 3 (C))
The timing signal applied to the WR terminal (Figure 3(b)
) and store it at the timing of the clock signal WCK, while the timing signal on the output side (Fig. 3 (f)
)) The stored data is output to the output terminal at the timing of the clock RCK on the output side. It is designed to be taken out at ut. In addition, FIG. 3(d) shows address A.
Represents a DR update.

In FIG. 1, the output iM of the selector 3 is applied to the data input terminal Din, the output signal of the selector 4 is applied to the 7'L1 timing terminal WR, and the output signal of the selector 4 is applied to the clock terminal WC.
KFC: ld person clock signal CLKi < Figure 2 (
a)) is marked. Therefore, the phase synchronization position fig
Input signal Si based on VC input signal CLK
It is temporarily stored in the elastane ink memory 7 in synchronization with i.

On the other hand, the pulse generation circuit 8 generates a clock signal CLi (
A frame signal sFo representing the first bit on the conversion side of the same 6-bit frame length as described above is applied to 7t, and a delay determination pulse SD for detecting the phase synchronization position of input data is generated based on these signals. 1 timing signal of elastic store memory 7 (RR terminal)
give.

Since the converting side clock signal CLKo is applied to the elastic store memory 70RCK terminal, the input data stored as described above is synchronized with the clock signals CI and Ko using the signal from the pulse generation circuit 8 as the starting point. Output terminal. You can read it from ut.

Here, the input side clock CLKi and the conversion side clock CLKo are kept at cylinder frequency, and the low speed input data S1 is passed through the elastic store memory 7.
can be converted into a digital sequence synchronized with the frame signal sFo on the conversion side at both speeds.

-Furthermore, the frame signal SFi on the input side and the 7-frame signal S1i''o on the conversion side have the same focus length of 1, but 6 bits,
They are not synchronized because their clocks are different.

Therefore, in order to accurately perform the above-mentioned low-speed → high-speed data conversion, the phase synchronization position must be determined to be positive 4:tM, and it must be performed quickly. Phase synchronization will be described below with full reference to FIG.

The clock signal CLKo (not shown) on the conversion side and the frame signal S are independent of the signals shown in FIGS.
F. (FIG. 2(J)), a delayed decision and a Luz SD are generated (FIG. 2(N)). This signal SD and signal S21
The timing is matched with any of steps S26 to S26.

Timing coincidence is taken at position 1 or 2 based on signals 821 to S26. In the case of 2, Ding, that is, S21
The signal SD is present in both consecutive pulses of ~S26.
In case c, there are two outputs from the A'ND gate 5, but the detection circuit 6 selects the slower one. In the case of one, the timing is output as the interphase Ju1 position signal S6 (61 in Fig. 2)). The time difference τ between SLI'i and the phase rotation position signal S6 is the input frame No. 11 S.
Fi time interval. This shows that the IaJ ratio can be detected within one frame of human power. In other words, synchronization detection does not lag in the next frame and synchronization detection can be performed continuously.If the time difference τ is within a predetermined time, the low-speed → high-speed data conversion via the elastic store memory described above can be performed. Since this can be done reliably, the detection circuit 6 applies the phase synchronization position signal s6 to the selectors 3 and 4 at the subsequent stage so that the input data is stored in the elastic store memory.

On the other hand, if the time difference τ is greater than or equal to a predetermined time, the phase synchronization detection operation is performed for the next input data. In this case, since the clock on the conversion side is at an island speed, phase synchronization detection can generally be performed in the next input frame.

The above phase synchronization detection detects the synchronization position on the input side so that it is synchronized with the conversion side link, and this detection breaks the characteristic that the input frame signal SFi is used as the reference rather than the input data Si. . Therefore, phase synchronization detection can be performed quickly and reliably regardless of the presence or absence of input data and its form.

The blade data string group (a)′(
b)(c)(d) are illustrated in FIG. 2(k). This signal S. It can be seen that the input signal Si is converted into a signal with a higher frequency than the input signal Si. A subsequent circuit multiplexes these signals and performs communication.

Effects of the Invention As described above, according to the present invention, it is possible to quickly detect the phase synchronization position of asynchronous input data, and furthermore, it is possible to accurately convert low-speed asynchronous input data into a high-frequency signal on the conversion side. can.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a signal synchronization/conversion device as an embodiment of the present invention, FIG. 2 is a signal timing diagram of the device shown in FIG. 1, and FIG.
FIG. 3 is a signal timing diagram showing the operation of the elastic store memory in the device shown in FIG. (Explanation of symbols) 1.2...Shift register, 3.4...Selector,
5... AND (""-), 6... Delay stage number detection circuit, 7... Elastic store circuit, 8... Pulse generation circuit.

Claims (1)

[Scope of Claims] A first register that sequentially receives a data string of a predetermined frame length and outputs a /'P pulse string in response to a predetermined clock; a frame indicating the beginning of a valley frame of the input data string; Signal 'If: The receiver responded to the predetermined signal p. +
a second register that outputs a 7 response string; a pulse generation circuit that generates a clock on the conversion side and a timing signal that rejects the beginning of each frame of the converted data string; A phase synchronization detection circuit that compares and detects the phase synchronization position,
and a memory for sequentially storing the output pulse train of the first register based on the phase synchronization position, and outputting the stored data in response to a clock on the conversion side based on a signal from the pulse generation circuit. Means, complete signal synchronization
conversion device.