JPS6043893A - Method of producing printed circuit board - Google Patents
Method of producing printed circuit boardInfo
- Publication number
- JPS6043893A JPS6043893A JP15181483A JP15181483A JPS6043893A JP S6043893 A JPS6043893 A JP S6043893A JP 15181483 A JP15181483 A JP 15181483A JP 15181483 A JP15181483 A JP 15181483A JP S6043893 A JPS6043893 A JP S6043893A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- forming
- printed wiring
- manufacturing
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 本発明は、プリント配線板の製造方法Vc胸するO 従来、導電性の八を南するプリント配線板は。[Detailed description of the invention] The present invention is a method for manufacturing a printed wiring board. Traditionally, printed wiring boards are conductive.
穴あけt行7t −z 7を後、穴部及びパッド部以外
の箇所のυr望パターンのレジスト形成、大内導体形成
2行なっていた。しかし、この方法ではレジスト形成時
にレジストのすnが生じると、大円がレジストで汚染さ
n7、又は穴上にレジストがかぷさり、大内導体形成が
困姫になるという入点を有してい7r。After drilling t rows 7t-z 7, resist formation of the desired pattern in locations other than the hole portions and pad portions, and two lines of Ouchi conductor formation were performed. However, this method has the disadvantage that when resist formation occurs during resist formation, the large circle is contaminated with resist, or the resist is covered over the hole, making it difficult to form the inner conductor. 7r.
本発明はこのよう7i:点VC鑑みてなさn、たもので
、穴あけ、穴部及びバッド都以外のi’、41 hfの
Qt望パターンのレジスト形成0表囲尋坏回路形成、大
内導体形成によって成るプリント配線板の製造方法にお
いて、FJTWiパターンのレジスト形成1行なっに後
に人あけ會行うこと【特数とするものである〇
本発明を図面により具体的に説明する0第1図に於て、
(a)銅張積層板(1)表囲にエツチングレジスト形成
俊、エツチングし尋体回路(2)に形成L、(b)スル
ーホール都およびランド部以外の部分にンルダーレジス
トに兼ねたレジスト(6)忙形成し、(C)穴(4)あ
けて行ない、(d)無電解めっきでスルーホールおよび
ランド部[41;卜5を形成する。The present invention is as follows: 7i: In view of point VC, hole drilling, resist formation of Qt desired pattern of i', 41 hf except for hole and bad capital, surface surrounding circuit formation, Ouchi conductor In the method of manufacturing a printed wiring board by forming a resist, an opening is carried out after one line of forming a resist for an FJTWi pattern. hand,
(a) Copper-clad laminate (1) Etching resist formed on the surface area, etching resist formed on the body circuit (2) L formed, (b) Resist that also served as an under resist on the parts other than through-hole capitals and land areas. (6) forming the holes, (C) drilling the holes (4), and (d) forming the through holes and land portions [41; 5] by electroless plating.
第2凶に於て、(a)依涜創(6)対基板(7)の表面
の所望部分にレジスト(5)τ形成し、(b)八(4)
めけ忙行ない、(C)無電解めっきで表面回路部および
スルーボール、ランド部VC導体(5)を形成し、(c
llレジストを剥pルしく行なわl〈てもよい)、(e
)←つソルダーレジス) (8) を形成丁ゐ〇第6図
に於て、(a)薄い銅箔(a)【付けた冶媒入り漉機表
向にレジスト(6)f形成し、(b)穴(4)ありτ竹
ない%(C)無゛屯解めっきと電気めっきで次曲回路部
およびスルーホール、ランド部に導体(5)、(8)τ
形成し、(d)レジスト剥tia、 (e)ソフトエッ
チを行なう。In the second step, (a) a resist (5) is formed on a desired portion of the surface of the opposing substrate (7) (6), and (b) eight (4)
After the plating process, (C) form the surface circuit part, through ball, and land part VC conductor (5) by electroless plating, and (c)
Peel the resist carefully (optional), (e
)←Solder resist) (8) Forming a resist (6) f In Figure 6, (a) Form a resist (6) f on the surface of the thin copper foil (a) b) With hole (4) τ without % (C) Conductor (5), (8) τ in the next curved circuit part, through hole, and land part by continuous plating and electroplating
(d) resist stripping and (e) soft etching.
第4図に於て、(a)杷緻OQ基板表面にH1蜜パター
ンのレジスト(6)形成で行ない、(b)ン((4)あ
けt行ない、(C)シーダー処!に行ない、 (d)レ
ジストr剥離し、(e)無電解めっきで表面回路部とス
ルーホール、ランド部に導体(5)を形成する。In Fig. 4, (a) H1 pattern resist (6) is formed on the surface of the dense OQ substrate, (b) (4) opening is done, (C) is being done in a seeder place, ( d) Peel off the resist r, and (e) form conductors (5) in the surface circuit area, through holes, and land areas by electroless plating.
以上説明し1ζようVC不発明に於ては、レジストリず
fLに共なう問題?C解決し、レジストJ′1゛谷ずn
重τ人さくでさる%1(7Jでレジストと穴の許容ずf
L負が穴径1.01佃1、ランド径1.2 mmの場会
現状の0.1能からiJ、 5 nunとなった。As explained above, in VC non-invention, is there a problem common to registry fL? Solve C, resist J'1'Valley's n
%1 (no tolerance for resist and holes in 7J)
When the negative L is 1.01 mm in hole diameter and 1.2 mm in land diameter, it becomes iJ, 5 nun from the current 0.1 capacity.
第1凶〜第4凶は不づ6明の刀びt示す藺凹凶である。 符号の説明 1、餉張稙層板 2、導体回路 6、 レジスト 4、入 5、導体 6、3≧F * Aす 7、基板 8、 ンルダーレジスト 9、電気めり@導体回路 1o、e緑基板 第3図 第4図 第1頁の続き 0発 明 者 山 野 井 清 下館市大字・所内 The 1st to 4th kyou are the raiko kyou that represent the sword of fuzu 6 ming. Explanation of symbols 1.Crystalline layer board 2. Conductor circuit 6. Resist 4. Enter 5. Conductor 6, 3≧F *A 7. Board 8. Ruder resist 9. Electric drilling @ conductor circuit 1o, e green board Figure 3 Figure 4 Continuation of page 1 0 shots Akira Yamano Ii Kiyoshi, Shimodate City, Oaza, premises
Claims (1)
望パターンのレジスト形成、表面専体回路形欣、大内導
体形成rCよって欣るプリント配線板の製造方法におい
て、所望パターンのレジスト形成紫行なった俊eζ尺あ
けr行うことr籍畝とするプリント配線板の製造方法。 2、人内専体形成r焦岨肩めっき音用いて行な′)g許
請求の範囲第1項aと載のヲリント配線板の製造方法。 3、表面導体i!21路形成r銅張撰層似tエツチング
することにより行う特許請求の範囲第1項記載のプリン
ト配線板の製造方法。 4、FA望パターンのレジストがソルダーレジストを兼
ねる特許請求の範囲第1項6已載りフ”リント配緋板の
製造方法。[Claims] 1. A method for manufacturing a printed wiring board, which includes forming holes, forming a resist with a desired pattern on the entry and pad portions, forming a dedicated circuit on the surface, and forming an internal conductor, A method for manufacturing a printed wiring board, which includes forming a resist with a desired pattern and then performing a spacing. 2. A method for manufacturing a printed wiring board according to claim 1(a), which is carried out using a special in-house forming method. 3. Surface conductor i! 21. The method of manufacturing a printed wiring board according to claim 1, which is carried out by forming a copper clad layer and etching it. 4. A method for producing a 6-layer printed thin strip board as claimed in claim 1, wherein the resist of the desired FA pattern also serves as a solder resist.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15181483A JPS6043893A (en) | 1983-08-19 | 1983-08-19 | Method of producing printed circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15181483A JPS6043893A (en) | 1983-08-19 | 1983-08-19 | Method of producing printed circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6043893A true JPS6043893A (en) | 1985-03-08 |
Family
ID=15526889
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15181483A Pending JPS6043893A (en) | 1983-08-19 | 1983-08-19 | Method of producing printed circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6043893A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01106496A (en) * | 1987-10-20 | 1989-04-24 | Asahi Chem Ind Co Ltd | Manufacture of through-hole circuit board |
JPH01194391A (en) * | 1988-01-28 | 1989-08-04 | Hitachi Chem Co Ltd | Manufacture of wiring board |
US7240431B2 (en) | 2004-10-27 | 2007-07-10 | Sharp Kabushiki Kaisha | Method for producing multilayer printed wiring board, multilayer printed wiring board, and electronic device |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5026022A (en) * | 1973-07-10 | 1975-03-18 | ||
JPS5260964A (en) * | 1975-11-14 | 1977-05-19 | Hitachi Ltd | Method of producing printed circuit board |
JPS5655099A (en) * | 1979-10-12 | 1981-05-15 | Fujitsu Ltd | Method of manufacturing printed board |
JPS5738040A (en) * | 1980-08-18 | 1982-03-02 | Mitsubishi Electric Corp | Signal transmitter |
JPS5773994A (en) * | 1980-10-27 | 1982-05-08 | Wako Denshi Kk | Method of securing metallic catalyst to printed circuit insulated board |
JPS58142598A (en) * | 1982-02-19 | 1983-08-24 | 日本電気株式会社 | Method of producing circuit board |
JPS59149091A (en) * | 1983-02-16 | 1984-08-25 | 松下電器産業株式会社 | Both-side printed circuit board and method of producing same |
-
1983
- 1983-08-19 JP JP15181483A patent/JPS6043893A/en active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5026022A (en) * | 1973-07-10 | 1975-03-18 | ||
JPS5260964A (en) * | 1975-11-14 | 1977-05-19 | Hitachi Ltd | Method of producing printed circuit board |
JPS5655099A (en) * | 1979-10-12 | 1981-05-15 | Fujitsu Ltd | Method of manufacturing printed board |
JPS5738040A (en) * | 1980-08-18 | 1982-03-02 | Mitsubishi Electric Corp | Signal transmitter |
JPS5773994A (en) * | 1980-10-27 | 1982-05-08 | Wako Denshi Kk | Method of securing metallic catalyst to printed circuit insulated board |
JPS58142598A (en) * | 1982-02-19 | 1983-08-24 | 日本電気株式会社 | Method of producing circuit board |
JPS59149091A (en) * | 1983-02-16 | 1984-08-25 | 松下電器産業株式会社 | Both-side printed circuit board and method of producing same |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01106496A (en) * | 1987-10-20 | 1989-04-24 | Asahi Chem Ind Co Ltd | Manufacture of through-hole circuit board |
JPH01194391A (en) * | 1988-01-28 | 1989-08-04 | Hitachi Chem Co Ltd | Manufacture of wiring board |
US7240431B2 (en) | 2004-10-27 | 2007-07-10 | Sharp Kabushiki Kaisha | Method for producing multilayer printed wiring board, multilayer printed wiring board, and electronic device |
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