JPS6043721B2 - ATC speed limit selection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a speed limit selection device for ATC (automatic train control) or ATC (automatic train stop device) using parallel dual-system receivers.

ATC (including ATS).

same as below. ) is a system that sends a signal from the ground to the track or loop in a certain section that specifies the train operating conditions in that section, and receives the ATC signal with an on-board receiver to control train operation. In order to improve reliability, it has been adopted to use a parallel dual system receiver for the ATC signal of each channel. A lower priority circuit is used that selects a safer speed limit when two or more channels of ATC signals are detected at the same time. However, in a conventional speed limit selection device using a parallel dual system receiver, when either the first system or second system detection circuit outputs a signal detection output, that output is input to the lower priority circuit. Therefore, when the detection circuit for a certain channel matches the actual transmission from the ground and outputs a signal detection output for both systems, at the same time, one system of the detection circuit for the other lower channel may malfunction. When the signal detection output is output, the signal detection output from the detection circuit that outputs the signal detection output for both systems from the lower priority circuit is not output as an ATC speed signal, and only the one system of the lower channel that malfunctioned. The signal detection output is AT
The signal is output as a C speed signal, resulting in a lack of color that results in unnecessary braking. This invention provides an ATC speed limit selection device using a parallel dual-system receiver.
If both channels are outputting signal detection outputs, eliminate the signal detection outputs of only one system due to malfunctions in other channels, and give priority to the signal detection outputs outputting from both systems. Moreover, if only one system is outputting a signal detection output in each different channel, or if both systems are outputting a signal detection output, unnecessary braking can be avoided by using the signal detection output of the lower channel as the ATC speed signal. The purpose is to eliminate such information and further improve the reliability of information. In order to achieve the above object, in the present invention, for each channel assigned for a preset speed limit, the signal detection output from the signal circuit from the two-system detection circuit for that channel is input. A first AND circuit, a first OR circuit that receives the signal detection output from the same two detection circuits, and inputs the output of this first OR circuit and the output of the first AND circuit provided for each channel. a second AND circuit that receives as input the output from the NOR circuit, and a second OR circuit that receives as input the output of the first AND circuit and the output of the second AND circuit. The output of the second OR circuit of the determination circuit operates the reception relay for the channel that constitutes the lower priority circuit.

Next, an embodiment of the present invention will be described based on the drawings.

■ is an ATC signal that is input via the on-board antenna, and is composed of multiple speed limit signals that determine train operating conditions, each of which is preliminarily set. It is transmitted based on the specified channel. RA and RB are first-system and second-system receivers, each consisting of detection circuits VlRA-VrlRA and VlRB-VnRB provided corresponding to the respective channels. Each detection circuit is the ATC signal of a specific channel! It has a built-in filter that only passes the ATC signal, and outputs a signal detection output when the ATC signal is detected. Two detection circuits VlRA and VlRB for each channel
, V2RA, V2RB-VnRA, and (1) RlRB are provided in parallel, so that the receivers RA and RB form a parallel duplex system. c1 to Cn are a pair of detection circuits VlRA, which are provided in duplicate for each channel, respectively.
This is a determination circuit connected to 1RB to VnRA and VI1RB, and all have the same configuration.

The configuration will be explained based on the determination circuit C1 as a representative example.
The determination circuit C1 includes a first AND circuit 1 to which the signal detection output of the first system detection circuit VlRA and the signal detection output of the second system detection circuit 1RB are input, and the two detection circuits 1RA.
, V1RB, and the output of the NOR circuit 5, which receives the output of the first AND circuit of the determination circuit provided for each channel. The second AND circuit 3 receives the output of the OR circuit 2, and the second OR circuit 4 receives the outputs of the first and second AND circuits 1 and 3.

The output of the second OR circuit 4 of each of the determination circuits c1 to Cn operates the receiving relays 1R-VnR provided for each channel.

The receiving relays VlR~■NR are designed to operate each contact that constitutes the known lower priority circuit D, and the lower priority circuit D corresponds to the ATC signal of each channel depending on which contact is activated. ATC speed output v1
~Vn is output. FIG. 2 shows a specific example of the determination circuit C1 and the NOR circuit 5 shown in FIG.
The signal detection output of the second system detection circuit VlRB is used as the collector input, the signal detection output of the second system detection circuit VlRB is made up of a transistor Trl used as the base input, and the emitter output is provided as the driving power for the reception relay VlR. , a NOR circuit 5 shared by each channel is configured by providing a relay R on the collector side of a transistor Tr2 to which the emitter output of the transistor of the first AND circuit 1 of the determination circuit of each channel is applied as a base. When the outputs of the two detection circuits 1RA and 1RB are input to the 2-AND circuit 3, the above-mentioned A movable contact of relay R is provided.

d1 to Dn are rectifying diodes. To explain the operation of such a configuration of the determination circuit, when the two-system detection circuits VlRA and 1RB of the first channel both output signal detection outputs, the transistor T of the first AND circuit 1
The input voltage is applied to the base of rl, and the transistor becomes 0N.
Then, the receiving relay VlR is operated by the output from the first system detection circuit VlRA.

At the same time, the emitter voltage of the transistor Trl, that is, the output of the first AND circuit 1 turns on the transistor Tr2 of the NOR circuit 5, so that the relay R is operated.
Therefore, since the second AND circuit 3 is opened, the output of the first OR circuit 2 is not applied to the receiving relay 1R. The relay R operates the movable contacts constituting the second AND circuits of all the determination circuits of the other channels. Therefore, if both detection circuits of one channel are outputting a signal detection output, and only one of the detection circuits of each pair of other channels outputs a signal detection output due to a failure, etc. , the second AND circuit 3 is prevented from satisfying the AND condition by relay R, so the reception relay for the channel is not operated.

In addition, when the first system detection circuit VlRA does not output and only the second system detection circuit VlRB outputs, the first AND circuit 1
does not output, so when there is no detection circuit of any other channel that the first and second systems output at the same time, relay R is restored and second AND circuit 3 is closed.
A reception relay VlR is operated by the signal detection output of the second system detection circuit VlRB.

If the detection circuits of multiple channels output both the first and second systems at the same time, or if the detection circuits of only one system of multiple channels output at the same time, the receiving relays corresponding to the channels are activated at the same time. However, in this case, the lower speed signal is transmitted to AT based on the lower channel reception relay by the lower priority circuit D mentioned above.
Selected as the C signal.

When the logic circuit shown in Fig. 1 is configured as in the embodiment shown in Fig. 2, the output voltage of the detection circuit is used as the driving power of the receiving relay, so there is no signal detection output of the detection circuit. Even if the logic circuit components fail in
The receiving relay never operates.

For example, conduction of transistor Trl, transistor T
If there is a failure such as open circuit r2, the desk, first and second system detection circuits V, RA. Of course, when neither V nor RB is output, the receiving relay VlR is not operated, but even if there is an abnormal signal detection output in one system, the subsequent lower priority circuit D outputs the upper signal. There isn't. Therefore, the fail-safe performance of the ATC receiving circuit is not impaired. As described above, according to the present invention, for each channel assigned for each speed limit, the first AND circuit receives the signal detection output from the two detection circuits for the channel, and a first OR circuit that receives the signal detection output from the system detection circuit; and an output from a NOR circuit that receives the output of the first OR circuit and the output of the first AND circuit provided for each channel. and a second OR circuit that receives the output of the first AND circuit and the output of the second AND circuit, and Since the output of the second OR circuit operates the reception relay for the channel that constitutes the lower priority circuit, when a high speed ATC signal is being transmitted, the detection circuit of the higher channel outputs both systems. However, when the detection circuit of the lower channel malfunctions and outputs only the saw system, the output of the detection circuit that outputs both systems is used as the ATC speed signal, so unnecessary braking is prevented. In addition, when the detection circuits of multiple channels output both systems, or when the detection circuits of multiple channels output only one system, the output of the detection circuit of the safe lower channel is reduced due to the action of the lower priority circuit. It is considered as an ATC speed signal.

Further, according to the invention described in the embodiment section, each component circuit of the determination circuit, the NOR circuit, and the reception relay use the signal detection output of the detection circuit of each channel as driving power, so when these fail, Since the reception relay is not operated, there is an advantage that fail-safety is further improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main parts of this invention, and the second
This figure is a circuit diagram showing a specific example of some of the circuits in FIG. 1. V...ATC signal, RA, RB...Receiver, VlRA~■NRA, VlRB-VnRB...
...detection circuit, c1 to Cn. ．． ．． ．． Judgment circuit, VlR
-, VnR... Reception relay, D... Lower priority circuit, 1... First AND circuit, 2...
・First OR circuit, 3...Second AND circuit (second
The figure also includes the invert conditions for the NOR circuit.

Claims (1)

[Claims] 1. In an ATC speed limit selection device using a parallel dual system ATC (including ATS; the same shall apply hereinafter) receiver, for each channel assigned for each control speed, two A first AND circuit that receives the signal detection output of the ATC signal detection circuit of the system, a first OR circuit that receives the signal detection output of the detection circuit of the two systems, and the output of this first OR circuit and each a second AND circuit that receives as input the output of the first AND circuit provided for the channel and the output from the NOR circuit that receives as input;
and a second OR circuit whose inputs are the output of the first AND circuit and the output of the second AND circuit, and the output of the second OR circuit of each determination circuit constitutes a lower priority circuit. A speed limit selection device for ATC, characterized in that receiving relays corresponding to each channel are operated respectively. 2. Each component circuit of the determination circuit, a receiving relay and a NOR circuit that share a channel with the determination circuit, uses the signal detection output of an ATC signal detection circuit that shares a channel with the determination circuit as driving power. The ATC speed limit selection device according to item 1.