JPS604355A - Interface system for transferring serial data - Google Patents

Abstract

PURPOSE:To detect DSR(Data Set Ready) by measuring a data transfer time and comparing the data transfer time with the preset maximum permissible value of the data transfer time. CONSTITUTION:When data are inputted, a receiving circuit 7 is set and sampling of data bits is started. Simultaneously, an interruption generating circuit 8 and counter 10 are set and the clock signal of a clock oscillator 9 is counted. The measured time is compared with the maximum permissible time preset in a setting circuit 11 at a comparator circuit 12 and, when the measured time becomes equal to the maximum permissible time, an abnormal signal is outputted for preventing reading of ''0'' signal under an abnormal condition as data.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a connection between a computer and a computer terminal,
The present invention also relates to an interface method used for connection between computers, and in particular, to an interface method for serial data transfer that makes it possible to detect abnormalities in a data transfer system.

[Prior art and its problems]

FIG. 1 shows an example of a serial data transfer system.

In FIG. 1, 1 is a data output device such as a keyboard, tape reader, printer, etc., 2 is a signal converter that converts parallel signals from the input/output device 1 into serial signals, and 3 is a CPU in a computer. It is.

4 sends the serial data input from the signal converter 2 to the CPU 3 via the signal line 5, or
This is an input/output interface that sends the output of U3 to the signal conversion device 2. Interface 4 generates a receive interrupt informing CPU 3 that input data is ready to be read.

In such a data transfer system, if the signal converter 2 fails or the signal line 5 is disconnected, normal data transfer becomes impossible. However, if the interface 4 does not have a means to detect this, the interface 4 will generate a reception interrupt just like when the system is normal, so the CPU 3 will receive the data incorrectly, and the CPU 3's function will be interrupted. Significantly decreased.

Therefore, in the conventional R5-232-C interface, the signal conversion device 2 is in a data transmission/reception enabled state (data
The signal DSR indicating that the
An abnormality in the system is detected by sending the DSR from the signal conversion device 2 to the interface 4, and the interface 4 receiving the DSR. However, this type of interface has the disadvantage that the number of signal lines increases by the number of signal lines for DSR transfer.

In addition, although a current loop type interface is known in the past, this type does not include a DSR detection means and has fewer signal lines.

However, this method has the drawback that the DSR of the signal conversion device 2 cannot be detected.

[Purpose of the invention]

It is an object of the present invention to eliminate the above-mentioned drawbacks of conventional interface systems of this type, and to use a current loop serial interface that can easily and reliably detect abnormalities in a data transfer system without increasing the number of signal lines. The object of the present invention is to provide an interface method for data transfer.

[Key points of the invention]

The present invention detects DSR by measuring the transfer time from the time the data start signal is received or from the fall of the signal due to an abnormality in the system, and comparing this measured time with a preset maximum allowable data transfer time. This is what I am trying to do.

[Embodiments of the invention]

FIG. 2 shows an interface circuit 6 according to one embodiment of the invention.

In the interface circuit 6, X is an input terminal connected to the signal converter 2, and 7 samples the value of each data bit of serial data input from the signal converter 2 through the input terminal X. This is a receiving circuit. 8
is an interrupt generation circuit that generates an interrupt request such as the above-mentioned reception interrupt, and the input terminal of the interrupt generation circuit 8 is connected to the output terminal of the reception circuit 7, and the serial data is generated when an interrupt is generated. It is also input to circuit 8, and interrupt generation circuit 8 is set.

9 is a clock oscillator, which is connected to the first input terminal of the NAND gate. 10 is a counter;
The output terminal of the receiving circuit 7 and the output terminal of the NAND gate are connected to the input terminal of the counter 10, and the serial data is also input to the counter 10.
is set/reset. set counter 10
measures the data sampling time of the receiving circuit 7 by counting the clock signals inputted from the clock oscillator 9 via the NAND gate NAND, and outputs the measured time.

Reference numeral 11 denotes a setting circuit in which the maximum number of data bits in serial data is set, and the maximum number of data bits is set as the maximum allowable data transfer time based on a constant data transfer rate.

12 is a comparison circuit, and the input terminal of the comparison circuit 12 is:
It is connected to the output terminal of the counter 10 and the output terminal of the setting circuit 11, and the comparison circuit 12 compares the measurement time of the counter 10 and the maximum allowable time of the setting circuit 11, and when both match, the comparison circuit 12 outputs an abnormal signal of “1”.

In order to prevent the clock signal from being input to the counter 10 while an abnormality in data transfer is detected, the output terminal of the comparison circuit 12 is connected to the second input terminal of the NAND via the inverter INV1. ing. In addition, the output terminal of the comparator circuit 12 is connected to the first input terminal of the AND gate AND via the inverter INVI, and the output terminal of the interrupt generation circuit 8 is connected to the first input terminal of the AND gate AND so that a reception interrupt request is suppressed when data transfer is abnormal. Output terminal is AND gate AN
It is connected to the second input terminal of D. An output terminal of the AND is connected to an output terminal Z.

Furthermore, in order to generate a data transfer abnormal interrupt, the output terminal of the comparison circuit 12 is connected to the output terminal Y via the inverters INv1 and NV2, and the output terminals Y and Z are
It is connected to cpU3 to forward interrupt requests.

FIG. 3 shows an example of the bit configuration of serial data.

FIG. 3(a) shows serial data when the signal converter 2 is normal, and a 1" signal is constantly applied to the interface 4 from the normal signal converter 2. The serial data consists of 1 bit. It begins with a start bit consisting of a long 0 signal, followed by a data bit of, for example, 10 bits long, consisting of a plurality of 1 or 0'' signals, and ends with a stop pit consisting of a 01'' signal of 1 bit length or more.

FIG. 3(b) shows the serial data when the signal converter 2 fails during data transfer. In FIG. Assuming that, from then on, a "0" signal is continuously outputted from the signal conversion device 2.

In the above configuration, when serial data is input to the interface circuit 6, the receiving circuit 7 is set by the start bit and starts sampling data bits. At the same time, the interrupt generating circuit 8 is set by the start bit and outputs a reception interrupt. At this time, since the output of the comparison circuit 12 is 0, a "1" signal is applied to the first input terminal of the AND gate AND through the inverter INV1, and the reception interrupt request is applied to the AND gate AND. and is input to the CPU 3 via the output terminal Z. The CPU 3 starts reading the sampling data of the receiving circuit 7 in accordance with the receiving interrupt request.

On the other hand, the counter 10 is set by the start bit of the serial data when the receiving circuit 7 starts sampling. At this time, as above, Nante Gate NAN
A 1" signal is applied from the inverter INV1 to the second input terminal of D, and the clock signal is applied to the clock oscillator 9.
The signal is input to the counter 10 via the NAND gate. The set counter 10 starts counting the clock signal, starts measuring the data sampling time of the receiving circuit, and constantly sends the measured time to the comparison circuit 12.

In the setting circuit 11, a maximum allowable time corresponding to 11 bits is set for serial data having a configuration as shown in FIG. 3(a), for example. This maximum allowable time is, for example, 1100 baud when the data transfer rate is 1100 baud.
Bit ÷ 1100 baud = 0.01 second.

The comparison circuit 12 compares this maximum allowable time of 0.01 seconds with the time measured by the counter 10.

When the signal conversion device 2 is normal, as shown in FIG. That is, when the measurement time is less than the maximum allowable time, the receiving circuit 7 and the counter 1
0 is reset.

As a result, the comparator circuit 12 does not output an abnormal signal of °1'', so it is detected that the DSR is on.

On the other hand, if the signal converter 2 fails during data transfer, as shown in FIG. 3 (1), for example, the serial data becomes a "0" signal from the middle of the data bit, and
The receiving circuit 7 and the counter 10 are not reset, and the measured time becomes equal to the maximum allowable time.

As a result, the comparator circuit 12 outputs an abnormal signal of 1",
The second input terminal of the NAND gate becomes “0”,
The clock signal is no longer input to the counter 10, the measurement time of the counter 10 is maintained equal to the maximum allowable time of the setting circuit 11, and the comparison circuit 12 continues to output an abnormal signal of 1''.

Therefore, the first input terminal of the AND gate AND is maintained at 0'', and the reception interrupt request (7) CI' in the abnormal state is
The input to U3 is suppressed, and CPLJ3 is erroneously
This prevents a "0" signal during an abnormality from being read as data.

Further, the 1° abnormality signal of the comparator circuit 12 is input as an abnormal interrupt request to the CPU 3 via the inverter INV1.2 and the output terminal Y, and it is detected that the DSR is off.

When the signal converter 2 returns to normal again and the ``1'' signal is applied to the input terminal The output becomes "0", an abnormal interrupt request to the CPU 3 is suppressed, and it is detected that the DSR is turned on.

Note that if the signal converter 2 fails while serial data is not being transferred, the receiving circuit 7 and the counter 10 is set, then the same operation as above is performed to detect whether the DSR is on or off.

Further, although the above embodiment relates to data transfer from a terminal device to a CPU, it is also possible to detect DSk using a similar circuit configuration in data transfer from a CPU to a terminal device or data transfer between CPUs. can.

〔Effect of the invention〕

As detailed in Section 2 below, in the present invention, the transfer time is often reduced from the time when a low voltage data start signal is received, or from the time when an abnormality occurs in the data transfer system and the signal falls to a low voltage. If the measurement time exceeds the preset data transfer allowable time,
By determining that the data transfer system is abnormal, the reception interrupt request to the CPU is suppressed, and the data transfer abnormal interrupt request is not sent to the CPU. This improves the functionality of the CI'U by protecting it from input to the CPU, and also improves the functionality of the DST.
In a current loop method that does not have an L detection means, it is possible to provide an interface method that enables DSR detection without adding a signal line.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a serial data transfer system, FIG. 2 is a block diagram showing an embodiment of the present invention,
FIG. 3 is a timing chart showing the structure of serial data. 2... Signal conversion device, 4... Interface, 5
...Signal line, 10...Counter, 12...Comparison circuit, 11...Setting circuit, Patent applicant: Fuji Electric Manufacturing Co., Ltd. Representative Patent Attorney Aoyama, 2 people

Claims (1)

[Claims] (1) When the data transfer system is normal, a normal signal maintained at a predetermined high level voltage is transferred, followed by a low level voltage data start signal and a data signal train, and then the above normal signal is transferred again. When the above system is abnormal, during serial data transfer in which an abnormal signal maintained at a low level voltage is transferred, measure the time from the time the data start signal is received or from the time the abnormal signal is received to the time the normal signal is received. Then, this measured time is compared with a preset maximum allowable transfer time for the data signal sequence, and if the measured time exceeds the maximum allowable transfer time, it is determined that the data transfer system is abnormal. An interface method for serial data transfer featuring: