JPS6042878A - Photo detector - Google Patents
Photo detectorInfo
- Publication number
- JPS6042878A JPS6042878A JP58151893A JP15189383A JPS6042878A JP S6042878 A JPS6042878 A JP S6042878A JP 58151893 A JP58151893 A JP 58151893A JP 15189383 A JP15189383 A JP 15189383A JP S6042878 A JPS6042878 A JP S6042878A
- Authority
- JP
- Japan
- Prior art keywords
- region
- light
- electrode
- substrate
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 239000012535 impurity Substances 0.000 abstract description 9
- 230000003321 amplification Effects 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 5
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 5
- 238000007667 floating Methods 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000002253 acid Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000035945 sensitivity Effects 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 150000007513 acids Chemical class 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の技術分野］
この発明は光検出器に関し、特に、半導体イメージセン
サのような光検出器における感度の改善に関する。TECHNICAL FIELD OF THE INVENTION This invention relates to photodetectors, and more particularly to improving sensitivity in photodetectors such as semiconductor image sensors.
［先行技術の説明］
従来より、半導体イメージセンサとしての光検出器は、
ｐ−ｎ接″合が多く用いられてきた。この光検出器は、
続出用トランジスタと直列に接続され、たとえばＭＯＳ
アドレス方式の場合は信号ラインに直接またはインター
ライントランスファ方式の場合にはＣＯＤに転送される
。[Description of Prior Art] Conventionally, a photodetector as a semiconductor image sensor is
A p-n junction has been widely used.This photodetector is
Connected in series with a transistor for continuous output, for example, a MOS
In the case of the address method, it is transferred directly to the signal line, or in the case of the interline transfer method, it is transferred to the COD.
第１図は従来の光検出器の構造を示す断面図である。第
１図において、たとえばｐ形のシリコンのような半導体
基板１には、ｎ形不純物領域２゜３が形成され、さらに
ポリシリコンなどによるＭＯＳトランジスタのゲート電
極４が形成される。FIG. 1 is a sectional view showing the structure of a conventional photodetector. In FIG. 1, an n-type impurity region 2.3 is formed in a semiconductor substrate 1 made of, for example, p-type silicon, and a gate electrode 4 of a MOS transistor made of polysilicon or the like is further formed.
ｐ形半導体基板１とｎ影領域２のｐｎ接合を光検出器と
して使用し、領域３を出力信号線として使用している。A pn junction between the p-type semiconductor substrate 1 and the n-shaded region 2 is used as a photodetector, and the region 3 is used as an output signal line.
このようなｐｎ接合による光検出器は、可視光において
高い量子効亭を有しており、良好な光検出器といえるが
、さらに感度を高めることにより、微弱光でも小さい光
検出器面積でも高い光′４流を得るためには改善が必要
とされる。A photodetector using such a pn junction has a high quantum efficiency in visible light and can be said to be a good photodetector, but by further increasing the sensitivity, it can be Improvements are needed to obtain optical '4 flow.
［発明の目的］
それゆえに、この発明の主たる目的は、ｐｏ光検出器よ
りも実効的に高い光検出能力を有する光検出器を提供り
ることである。[Object of the Invention] Therefore, the main object of the present invention is to provide a photodetector that has an effectively higher light detection ability than a PO photodetector.
この発明の上述の目的およびその他の目的と特徴は以下
に図面を参照して行なう詳細な説明から一層明らかとな
ろう。The above objects and other objects and features of the present invention will become more apparent from the detailed description given below with reference to the drawings.
［発明の概要］
この晃明を要約すれば、第１の導電形式の半導体駐根上
に、この基板と逆導電形式の第１の領域を形成し、この
第１の領域中に基板と同一導電形式の第２ないし第４′
の領域を形成し、第２および第３の領域をそれぞれＭＯ
Ｓトランジスタ・のドレインとソースとし、第４の領域
を第３の領域に隣接して形成し・、上部から少なくとも
第１．第３および第４の領域の一部に光が入射したとき
光電流を増幅倍し、ＭＯＳトランジスタを介して第２の
領域から読出すように構成した光検出□器である。[Summary of the Invention] To summarize this invention, a first region of a conductivity type opposite to that of the substrate is formed on a semiconductor base of a first conductivity type, and a conductivity type of the same conductivity type as that of the substrate is formed in this first region. 2nd to 4th' of
, and the second and third regions are each MO
A fourth region is formed adjacent to the third region, and at least the first...S transistor is formed adjacent to the third region. The photodetector is configured to amplify the photocurrent when light is incident on a portion of the third and fourth regions, and read it out from the second region via a MOS transistor.
、「１発明の実施例」 第２図はこの発明の一実施例の縦断面図である。, "1 Example of the invention" FIG. 2 is a longitudinal sectional view of an embodiment of the present invention.
第２図において、ｎ形シリコン基板１の上面にはｐ形不
純物鎖酸２が形成される。このｐ形不純物領域２には、
ｎ形不純物鎖酸３，４．５がそれぞれ形成される。さら
に、ｐ形不純物領域２の上部にはポリシリコン層のＭＯ
Ｓトランジスタのゲート電極が形成される。なお、前述
のｎ形不純物領域３および５にはそれぞれ金属電極８，
７が接触するように形成される。In FIG. 2, a p-type impurity chain acid 2 is formed on the upper surface of an n-type silicon substrate 1. In this p-type impurity region 2,
N-type impurity chain acids 3 and 4.5 are formed, respectively. Furthermore, a polysilicon layer MO
A gate electrode of the S transistor is formed. Note that metal electrodes 8 and 5 are connected to the n-type impurity regions 3 and 5, respectively.
7 are formed so that they are in contact with each other.
次に、動作原理について説明する。第２図に示す光検出
器はいわゆる蓄積電荷方式で使・用される。Next, the principle of operation will be explained. The photodetector shown in FIG. 2 is used in a so-called accumulated charge method.
すなわち、ｎ影領域４に充１１１１荷を与えるため、ｎ
形編域３をプラス電圧に設定し、ゲート電極６にはたと
えｌ；ｊ５Ｖのプラス電圧パルスを印加する。That is, in order to give a charge of 1111 to n shadow region 4, n
The shape region 3 is set to a positive voltage, and a positive voltage pulse of, for example, l;j5V is applied to the gate electrode 6.
これによって、ＩＩ形領領域４３Ｖｌ）ｉ！度のフロー
ティング電位に設定することができる。次に、上部から
ｎ影領域４，５およびｐ影領域２め一部に光９を照射す
る。すると、ｎ形！ｉ域４の充Ｎｗｌ荷が放電を開始す
る。この放電による電荷の減少は、照射光の強さと時間
とに比例、する。照射光の強度が同じでもできるだけ早
く充電電荷が放電するためには、光９の照射によって発
生したキャリアがさらに増幅されることが好ましい゛。As a result, the II-shaped area 43Vl)i! Can be set to a floating potential of degrees. Next, light 9 is irradiated from above onto the n-shade areas 4 and 5 and a part of the p-shade area 2. Then, n-type! The charged Nwl load in i-area 4 starts discharging. The decrease in charge due to this discharge is proportional to the intensity and time of the irradiated light. In order to discharge the charged charges as quickly as possible even if the intensity of the irradiated light is the same, it is preferable that the carriers generated by the irradiation with the light 9 be further amplified.
この増幅効果を与えるための１つのバイアス電圧印加例
は、基板１を接地電極７にプラス電位を与えることであ
る。ｐ影領域２は若干のプラス電位（たとえば０．５Ｖ
）または７０−ティング電位とする。光９は上部からｐ
影領域２に入射する。One example of applying a bias voltage to provide this amplification effect is to apply a positive potential to the ground electrode 7 of the substrate 1 . The p shadow region 2 has a slight positive potential (for example, 0.5V
) or 70-Ting potential. Light 9 is p from the top
It is incident on shadow region 2.
可視長波長などの一部は１形餉域４または５を透過して
ｐ形領［２に入射されることもある。゛ｐ形輌域２に入
射した光は正孔、電子対を発生し、電子はｎ影領域５ま
たは４に注入される。一方、正孔はｐ影領域２からｎｆ
Ｆ３１１１ｉ域１に注入される。同時に、ｎ形側１から
小数キャリアとして電子がｐ影領域２に注入され、さら
にｎ影領域４に吸入され、これが充電電荷の放電に寄与
する。A part of the visible long wavelength may pass through the type 1 region 4 or 5 and enter the p type region [2. Light incident on the p-type region 2 generates holes and electron pairs, and the electrons are injected into the n-shade region 5 or 4. On the other hand, holes flow from p shadow region 2 to nf
Injected into F3111i area 1. At the same time, electrons are injected as minority carriers from the n-type side 1 into the p-shaded region 2 and are further sucked into the n-shaded region 4, which contributes to the discharge of the charged charge.
光によって誘起された正孔電流は、１果としてｎ影領域
４のコレクタ、ｐ影領域２で形成されるベース、ｎ影領
域１のエミッタで形成されるｎｐｎトランジスタの電流
増幅亭倍されることになる。The hole current induced by light is multiplied by the current amplification of the NPN transistor formed by the collector of the N-shaded region 4, the base formed by the P-shaded region 2, and the emitter of the N-shaded region 1. become.
この光の照射量に比例した放電電荷量は、ＭＯＳトラン
ジスタのゲート電極６にパルスを印加することにより、
電極８から読出される。By applying a pulse to the gate electrode 6 of the MOS transistor, the amount of discharge charge proportional to the amount of light irradiation can be
It is read out from electrode 8.
他のバイアス電圧印加方法としては、ｎ形基板１にプラ
ス電圧（たとえば５Ｖ）、Ｗ極７を接地する。但し、ｐ
影領域２は若干のプラス電位またはフローティングとす
る。このとき、前述の説明と同様にして、上部からｐＷ
３領域に光を入射する。Another bias voltage application method is to apply a positive voltage (for example, 5 V) to the n-type substrate 1 and ground the W pole 7. However, p
The shadow area 2 is set to a slightly positive potential or floating. At this time, in the same manner as described above, pW
Light is incident on three areas.
この光入射によって発生した電子、正孔対のうち電子ま
たはｎ影領域４またはｎ形基板１に吸収され、正孔はｎ
影領域５に注入される。この正孔の注入に対応してｎ形
鋼１１５からｐ影領域２に電子が注入され、これがｎ影
領域４に到達する。この場合は光によって発生した正孔
電流が、結果としてｎ影領域４をコレクタ、ｒＩ形領領
域２ベース。Of the electron and hole pairs generated by this light incidence, the electrons or n-type substrate 1 are absorbed by the n-shade region 4 or the n-type substrate 1, and the holes are n
Injected into the shadow area 5. In response to the injection of holes, electrons are injected from the n-shaped steel 115 into the p-shaded region 2, and these electrons reach the n-shaded region 4. In this case, the hole current generated by the light results in the n-shape region 4 being the collector and the rI-type region 2 being the base.
−影領域５をエミッタとするラテラルトランジスタの電
流増幅率倍されることとなる。- The current amplification factor of the lateral transistor whose emitter is the shadow region 5 will be multiplied.
［発明の効果］
以上のように、この発明によれば、従来のｐｎ接合フォ
トダイη−ドに比べ、その光検出感度を実効的に１ｌｉ
ｌＰＩ＆増幅率倍させることができる構造を提供するこ
とができる。なお、この発明による構造は従来のシリコ
ン半導体１．造技術で容易に実現できる。[Effects of the Invention] As described above, according to the present invention, compared to the conventional pn junction photodiode, the photodetection sensitivity is effectively increased to 1li.
A structure capable of multiplying lPI & amplification factor can be provided. Note that the structure according to the present invention is different from the conventional silicon semiconductor 1. This can be easily achieved using construction technology.
第１図は従来の光検出器の断面図である。第２図はこの
発明の〜実施例の縦断面図である。
図において、１はｎ形シリコン基板、２はｐ形不純物鎖
酸、３．４．５はｎ形不純物領域、６はポリシリコン編
のＭＯＳ トランジスタゲート電極７は金ｍｗ１極を示
づ。
代 理 人 大 岩 増 雄
第１図
第２図
手続補正書（自発）
ｂ・許庁長宮殿
１、事件の表示 特願昭５８−１５１８９３号２、発明
の名称
光検出器
３、補正をする者
５、補正の対象
明細書の発明の詳細な説明の欄
６、補正の内容
明細書の第５頁第１０行の「可視艮波艮」を「可視の長
波長光」に訂正する。
以上FIG. 1 is a cross-sectional view of a conventional photodetector. FIG. 2 is a longitudinal cross-sectional view of embodiments of the present invention. In the figure, 1 is an n-type silicon substrate, 2 is a p-type impurity chain acid, 3.4.5 is an n-type impurity region, 6 is a polysilicon MOS transistor gate electrode 7 is a gold mw1 pole. Agent Masuo Oiwa Figure 1 Figure 2 Procedural amendment (voluntary) b. Office Minister Palace 1, case indication Patent Application No. 151893/1989 2, name of invention photodetector 3, amendments made Complainant 5, in Column 6 of the Detailed Description of the Invention in the Specification Subject to Amendment, on page 5, line 10 of the Specification of Contents of the Amendment, ``visible light wave'' is corrected to ``visible long wavelength light.''that's all
Claims (1)
体基板に対して逆導電形式の第１の領域と、 前記第１の領域中に前記半導体基板と同一導電形式の領
域によって形成される第２′ないし第４の領域とを含み
、 前記第２おより第３の領域は、それぞれＭＯＳトランジ
スタのドレインとソースとを構成し、前記第４の領域は
前記第３の領域に隣接して形成されていて、 Ｅ部から少なくとも前記第１．第３および第４の領域の
一部に光が入射したとき、光電流を増幅値し、前記ＭＯ
Ｓトランジスタを介して前記第２の領域から続出すよう
にした、光検出器。[Scope of Claims] A first region formed on a semiconductor substrate of a first conductivity type and having a conductivity type opposite to the semiconductor substrate; and a conductivity type same as that of the semiconductor substrate in the first region. 2' to 4th regions formed by the MOS transistor, the second to third regions constitute a drain and a source of the MOS transistor, respectively, and the fourth region is formed by the third region. is formed adjacent to the region of at least the first. When light is incident on part of the third and fourth regions, the photocurrent is amplified and the MO
A photodetector connected successively from the second region via an S transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58151893A JPS6042878A (en) | 1983-08-18 | 1983-08-18 | Photo detector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58151893A JPS6042878A (en) | 1983-08-18 | 1983-08-18 | Photo detector |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6042878A true JPS6042878A (en) | 1985-03-07 |
Family
ID=15528496
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58151893A Pending JPS6042878A (en) | 1983-08-18 | 1983-08-18 | Photo detector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6042878A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4801991A (en) * | 1987-07-17 | 1989-01-31 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor light receiving device |
-
1983
- 1983-08-18 JP JP58151893A patent/JPS6042878A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4801991A (en) * | 1987-07-17 | 1989-01-31 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor light receiving device |
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