JPS6042664A - Testing device for integrated circuit device - Google Patents

Testing device for integrated circuit device

Info

Publication number
JPS6042664A
JPS6042664A JP58150763A JP15076383A JPS6042664A JP S6042664 A JPS6042664 A JP S6042664A JP 58150763 A JP58150763 A JP 58150763A JP 15076383 A JP15076383 A JP 15076383A JP S6042664 A JPS6042664 A JP S6042664A
Authority
JP
Japan
Prior art keywords
test
value
cpu3
test items
statistical data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58150763A
Other languages
Japanese (ja)
Inventor
Yasushi Matsukawa
靖 松川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58150763A priority Critical patent/JPS6042664A/en
Publication of JPS6042664A publication Critical patent/JPS6042664A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits

Abstract

PURPOSE:To shorten a test time and to reduce the cost of the test by guaranteeing the manufacture quality of a lot on the basis of statistical data on a specific quantity of measured values, and then omitting the guaranteed test items about the remaining quantity. CONSTITUTION:A CPU3 controls a measuring part 5 according to a test program 7 in a storage part 4 to test bodies 6 to be tested about all test items. Measured values are stored in measured value storage parts 101-, and the total number of tests and the quantity of conforming articles are stored in storage parts 8 and 9 of counters. The CPU3 interrupts the test temporarily when the number of conforming article attains to a set value to calculate the yield, and then obtains statistical data on the mean value, standard deviation, maximum value, minimum value, etc., of every test item. A host computer part 1 compares the past data with a reference value to inform the CPU3 of whether individual test items are omitted or not. The CPU3 edits the program 7 so as to jump test items which can be omitted, and restarts the test.

Description

【発明の詳細な説明】 本発明は半導体集積回路等の試験装置に関する。[Detailed description of the invention] The present invention relates to a testing device for semiconductor integrated circuits, etc.

最近、半導体集積回路は大規模化が著しく、これに伴い
、試験装置は高機能化、複雑化、尚価格化しておシ、ま
た試験項目数および試験時間は非常に増大してきている
ので試験コストの増大が激しい。
Recently, the scale of semiconductor integrated circuits has increased significantly, and as a result, test equipment has become more sophisticated, complex, and expensive.Also, the number of test items and test time have increased significantly, resulting in test costs. is rapidly increasing.

一般に、半導体集積回路等を試験検査するKは、試験装
置が使用され、個々の品棟に応じて、試験条件、試験項
目および試験の11序流れを定義する試験プログラムが
準備され、これに基すき、半導体集積回路等の被試験物
は通常全数、試験検査され、良・不良の判定がなされる
Generally, in testing and inspecting semiconductor integrated circuits, etc., test equipment is used, and a test program is prepared that defines test conditions, test items, and the flow of the test according to each product building. All test objects, such as semiconductor integrated circuits, are normally tested and inspected to determine whether they are good or bad.

しかしながら前述したように試験装置は高価格化し、一
方被試験物の試験項目数は増大し、試験時間は著しく増
大しているので、試験装置の処理量は低下、試験コスト
の増大をまねいている。
However, as mentioned above, test equipment has become more expensive, the number of test items on test objects has increased, and testing time has increased significantly, resulting in a decrease in the throughput of test equipment and an increase in testing costs. .

本発明はこのような問題点を解決する試験方法および試
験装置を提供するものである。
The present invention provides a test method and a test device that solve these problems.

従来、半導体集積回路等の試験は第1図の流れ図に示す
ように、良品については第1テストから第へテストまで
全項目についてなされてきた。ところが、半導体集積回
路等の製造技術の進歩は著しく、非常に筒い歩留シを安
定して示すようになってきたこと、また半導体集積回路
寺の製造プロセスは基本的にバッチ処理であり、同一ロ
ット内の半導体集積回路等は、同様の特性を示すことに
より、Nテスト項目中のいくつかのテストについては、
敢終結来が不良であるものも含めて、10ツトのテスト
結果がすべて良いということが、しばしはである。
Conventionally, tests for semiconductor integrated circuits and the like have been performed on all items from the first test to the second test for non-defective products, as shown in the flowchart of FIG. However, the manufacturing technology for semiconductor integrated circuits has made remarkable progress, and it has become possible to stably exhibit extremely high yield rates.The manufacturing process for semiconductor integrated circuits is basically a batch process. Semiconductor integrated circuits, etc. in the same lot exhibit similar characteristics, so some of the tests in the N test items are
It is often the case that all 10 test results are good, including those with poor final results.

ネ発明はこの点に注目して試験コストの低減全目的とし
たものである。
The present invention focuses on this point and aims to reduce testing costs.

歩留シや測定1面をもとに製属プロセスを管理し、ロフ
トの製造品質を4i!i−足し、テスト結果がすべて良
であると予想されるテストについては、前述の理由によ
り試験を省略することが可能と判萌される。
Manage the metal manufacturing process based on the yield rate and one measurement, and improve the manufacturing quality of lofts to 4i! For the tests for which all test results are expected to be good, it is determined that the tests can be omitted for the reasons mentioned above.

本発明の特徴は、半導体集積回路等の試験方法および試
験装置において、10ツト中の所定の数量について全テ
スト項目を試験し、歩留りおよび画定値の平均値、標準
偏差等の統計データを得る4段と、前記歩留りおよび測
定値の統計データが所定の基準値内にあるかどうか、ま
た、過去に試験したロフトの歩留りおよび測定値の統計
データの分布において所定の範囲内Vcあるかどうかを
比軟判定する手段と、前記比較判定結果よ)、基準値内
また範囲内にあるテスト項目をジャンプする手段とを備
え、残シの数量については前記ジャンプされたテスト項
目を試験しない試駆方法および試験装置にめる。
A feature of the present invention is that in a test method and test apparatus for semiconductor integrated circuits, etc., all test items are tested for a predetermined number of 10 tests, and statistical data such as the average value and standard deviation of the yield and defined values are obtained. and whether the statistical data of the yield and measured values are within a predetermined standard value, and whether Vc is within a predetermined range in the distribution of the statistical data of the yield and measured values of lofts tested in the past. and means for making a soft judgment (based on the comparison judgment results), and means for jumping test items that are within the reference value or within the range, and a trial driving method that does not test the jumped test items with respect to the remaining quantity. Place in test equipment.

以下、本発明の一実施飼を第2図に示す。1はホストコ
ンピュータ部、2は試験部で中央処理装*(以下CPU
と略す)3、記憶部4、測定部5からなシ、6は被試験
物である。CPU3は配憶4の中に格納されている試験
プログラム7の内容に基すき測定部5を制御し、被試験
物6を試験し区鋏結釆を記憶部4に格納する。10ツト
の試験開始後所定の数量例えば良品数がP個に達するま
では、従来どおり全テスト項目について試験がなされ、
かつ測定値、例えば、入力電流値、出力電圧値、アクセ
スタイム値等が、それぞれのテスト項目省焉に応じて、
測定i脩fi&1部10.、10.・・・・・・1 o
NKg納され、また試験総個砂と良品数は各各カウンタ
ー動作の格納部8と9に格納される。JCPU3は良品
数格納部9の内容が、あらかじめ設定された数値PK達
した時点で、次の被試験物の試験を一時中断し、P(L
!1についての試験結果の処理に移シ、良品数格納部9
の内容を試験総個数格納部8の内容で除し、歩留りをめ
、次いで、測定値格納部10.、10.、・・・ION
それぞれの内容を読み出し、テスト項目ごとに平均値、
標準偏差、最大値、最小値等の統計データをめた後、ポ
スストコンピュータ部1へ歩留シ値および統計データを
送る。ホストコンピュータ部1においては、送られてき
た歩留シ値および統1テータを記憶部11に格納すると
lh]時に、過去のlbJ休のテークの統計データつま
り、歩留り各6i11 kテークの平均値標準偏差、最
大値、最小1i%のテークとの比軟およびめらかじめ設
定されている基準1illとの比軟を5− 行い、例えは歩留シが基準値以上であり、かつ過去の歩
Mb分布において安定の範囲内にあること、個々のテス
ト項目について、画定値の平均値標準偏差等が基準値よ
シ良く、かつ過去の平均値標準偏差等の分布において、
庚足の範囲内にめること等の判定を行い、判足結来つま
シ、イ向々のテスト項目のテスト省略の可否をCPU3
へ送る。CPU3はこの結果に基すき、テスト省略可能
なテスト項目については、そのテスト項目をジャンプす
るように、試験プログラム7を編果し、一時中断してい
た試験を再開する。つま夛以降の被試験物の試験は、全
テスト項目について試験はなされず、いくつかのテスト
項目は省略されることになる。
One example of feeding according to the present invention is shown in FIG. 2 below. 1 is the host computer section, 2 is the test section and the central processing unit* (hereinafter referred to as CPU)
(abbreviated as) 3, storage section 4, measurement section 5, and 6 are test objects. The CPU 3 controls the clearance measuring section 5 based on the contents of the test program 7 stored in the storage section 4, tests the test object 6, and stores the results of the test on the test object 6 in the storage section 4. After the start of the 10 test, all test items are tested as before until a predetermined quantity, for example, the number of non-defective products reaches P.
And the measured values, such as input current value, output voltage value, access time value, etc., are changed according to the reduction of each test item.
Measurement i 脩fi & 1 part 10. , 10.・・・・・・1 o
The total number of pieces tested and the number of non-defective pieces are stored in the storage sections 8 and 9 of each counter operation. When the contents of the non-defective number storage section 9 reach the preset value PK, the JCPU 3 temporarily suspends the test of the next test object and returns P(L).
! Moving on to processing the test results for 1, the number of non-defective products storage section 9
The content of . , 10. ,...ION
Read each content and calculate the average value for each test item,
After collecting statistical data such as standard deviation, maximum value, minimum value, etc., the yield value and statistical data are sent to the post computer section 1. In the host computer section 1, when the sent yield value and standard data are stored in the storage section 11, the statistical data of past lbJ holidays' takes, that is, the average value standard of each 6i11 k take, is stored. The deviation, the maximum value, the ratio with the minimum 1i% take, and the ratio with the standard 1ill set for smooth dampness are calculated. The Mb distribution must be within a stable range, the average standard deviation of the delimited values for each test item must be better than the reference value, and the past average standard deviation, etc. must be within a stable range.
The CPU 3 makes judgments such as whether the foot is within the range of the foot, and determines whether or not to omit the test items for the foot and the foot.
send to Based on this result, the CPU 3 edits the test program 7 to jump to the test item for which the test can be omitted, and resumes the temporarily suspended test. In the tests of the test objects after the final test, all test items will not be tested, and some test items will be omitted.

従って、試験時間は省略されるテスト項目数に応じて短
りちれることになる。
Therefore, the test time is shortened according to the number of test items that are omitted.

以上説明し罠ように、本発明に工れば、10ツトの所定
の数量の画定値の統計テークにより、そのロフトの製造
品質を保証した上で、保証されたテスト項目を残シの数
量について省略するわけで、#!造品質が安定している
かぎり、試1時間は大幅6− に短縮されることになり、試験コスト低減への寄与は著
しい。
As explained above, if the present invention is implemented, the manufacturing quality of the loft is guaranteed by statistical analysis of the predetermined values of 10 predetermined quantities, and the guaranteed test items are applied to the remaining quantities. I will omit the #! As long as the manufacturing quality is stable, the test time can be significantly shortened to 6 hours, making a significant contribution to reducing test costs.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の試験プログラムの流れ図、第2図は本発
明の一笑施ψI」を示すブロック図である。 なお図において、1・・・・・・ホストコンピュータ都
、2・・・・・・試験*+i、3・・・・・・中央処塊
装敢、4・・・・・・記憶部、訃・・・・・測定部、6
・・−・・・被試験物、7・・・・・・試験プログラム
格納部、8・・・・・・試験総個数格納部、9・・・・
・・良品数格納部、10..102.10□、・・・1
ON・・・・・・がり定11Il栢Wj首is、11・
・・・・・h己憶都である。 7− 第1図
FIG. 1 is a flowchart of a conventional test program, and FIG. 2 is a block diagram showing the implementation of the present invention. In the figure, 1...Host computer, 2...Test *+i, 3...Central storage unit, 4...Storage unit, ...Measurement section, 6
...... Test object, 7... Test program storage section, 8... Total test number storage section, 9...
...Non-defective product storage section, 10. .. 102.10□,...1
ON...... Gari 11 Il Kaya Wj neck is, 11.
・・・・・・It is my memory. 7- Figure 1

Claims (1)

【特許請求の範囲】[Claims] 半導体集積回路等の試験装置において、10ツト中の所
定の数量について全テスト項目を試験して歩留シおよび
測定値の平均値、標準偏差等の統計データを得る手段と
、前記歩留シおよび測定値の統計データが所定の基準値
内にあるかどうか、および過去に試験したロシトの歩留
9および測定値の統計データの分布において所定の範囲
内にあるかどうかを比較判定する手段と、前記比較判定
結果よシ所定の基準値内もしくは所定範囲内にあるテス
ト項目をジャンプする手段とを備え、残シの数量につい
ては、前記ジャンプされたテスト項目を試験しないこと
を特徴とする集積同略装値の試験装置。
In a testing device for semiconductor integrated circuits, etc., means for testing all test items on a predetermined number of 10 tests to obtain a yield chart and statistical data such as the average value and standard deviation of the measured values; means for comparing and determining whether the statistical data of the measured values are within a predetermined reference value and whether the distribution of the statistical data of the Rosito yield 9 and the measured values tested in the past is within a predetermined range; means for jumping test items whose comparison and judgment results are within a predetermined reference value or within a predetermined range, and with respect to the remaining quantity, the jump test items are not tested. Abbreviated test equipment.
JP58150763A 1983-08-18 1983-08-18 Testing device for integrated circuit device Pending JPS6042664A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58150763A JPS6042664A (en) 1983-08-18 1983-08-18 Testing device for integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58150763A JPS6042664A (en) 1983-08-18 1983-08-18 Testing device for integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6042664A true JPS6042664A (en) 1985-03-06

Family

ID=15503877

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58150763A Pending JPS6042664A (en) 1983-08-18 1983-08-18 Testing device for integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6042664A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5469220A (en) * 1993-09-21 1995-11-21 Sharp Kabushiki Kaisha Vertical synchronizing circuit
US6151695A (en) * 1998-02-13 2000-11-21 Mitsubishi Denki Kabushiki Kaisha Test method of chips in a semiconductor wafer employing a test algorithm

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5469220A (en) * 1993-09-21 1995-11-21 Sharp Kabushiki Kaisha Vertical synchronizing circuit
US6151695A (en) * 1998-02-13 2000-11-21 Mitsubishi Denki Kabushiki Kaisha Test method of chips in a semiconductor wafer employing a test algorithm

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