JPS6041781B2 - Memory access method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a data processing system in which a plurality of data processing devices commonly use a specific area of one storage device. The present invention relates to a write control method when accessing the storage device from any one of the storage devices and rewriting only a part of the bit field of the storage word stored therein.

Used in a data processing system in which the plurality of data processing devices described above share a specific area of the storage device as a communication area and mutually exchange information via stored words stored in this communication area. .

Specifically, there is a line scanning unit that disassembles and generates transmission and reception bits for a large number of lines and disassembles and assembles transmission and reception characters, and a character processing unit that processes characters to be assembled and disassembled using a program. The scanning section and the character processing section are used in a communication control device that exchanges information between them via one data storage device. In a conventional communication control device, especially when a large number of lines are accommodated, a storage device used by a line scanning unit and a transmitting/receiving unit are used for line scanning, disassembling and generating transmitting/receiving bits, and disassembling and assembling transmitting/receiving characters. and a separate storage device used by the character processing section to process the characters, which makes the exchange of data and control information between the two storage devices complicated. was.

To avoid this, a single storage device is used, and this one storage device is divided in time between the line scanning section and the character processing section, and a specific storage area of the storage device is used by the line scanning section. A storage system has been devised and put into practical use that is shared as a communication area for exchanging data, data, and control information between the character processing unit and the character processing unit. However, if such a storage method is adopted, one storage device is used in a time-sharing manner by the line scanning section and the character processing section, so for example, the storage device is accessed from the character processing section. When rewriting only the contents of some bit fields of the stored word in the communication area, the character processing unit reads the stored word at the first access time assigned to the character processing unit, When it is necessary to rewrite the target bit field and store the partly rewritten storage word in the original storage position again in the second access time allocated to the character processing section,
Between the first access time and second access time assigned to the character processing section, there is a third access time assigned to the line scanning section, and at that access time, the line scanning section The data that needs to be transmitted to the character processing unit at the above storage location, the generation of transmission/reception bits, and the results of updating the counters provided on the storage word for assembling and disassembling the transmission/reception characters. Even if the stored word is stored, the information stored from the line scanning unit at the third access time by the subsequent re-storage of the stored word using the second access time from the character processing unit. A rift occurs in which the information is lost.

Such an event is not limited to a single communication control device, but rather occurs when multiple zeta processing devices, which execute data processing independently of each other, use one storage device in a temporally divided manner. A part or all of the storage area of the storage device is shared as a communication area, and information is exchanged between a plurality of data processing apparatuses via the storage words stored in this communication area. A similar phenomenon may occur in general data processing systems in which information is exchanged between a plurality of data processing devices using a so-called memory coupling method. In order to prevent this, conventionally, in general data processing systems, in such a case, until the re-storage of the stored word by the J second access time is completed, the third access time is Access to the storage device, especially write access to the communication area, was prohibited. However, by doing so, a plurality of memory-coupled data processing devices cannot access the storage device completely independently of each other. Particularly in communication control equipment, there is a situation in which, in order to assemble and disassemble transmitting and receiving characters, the line scanning section must generally be guaranteed access to the storage device at a certain period. For this purpose, data and control information are exchanged between the line scanning section and the character processing section using a memory coupling method using one storage device, and the line scanning section and the character processing section perform their respective data processing independently of each other. This has been a constraint in realizing a communication control device that performs this. An object of the present invention is to allow a plurality of data processing devices that perform data processing independently of each other to use one storage device in a time-divided manner, and to store part or all of the storage device. In a data processing system where an area is shared as a communication area and information is exchanged between multiple data processing devices via storage words stored in this communication area, each data Means by which the processing devices can freely access the storage device at the access time allocated to each data processing device of the storage device, regardless of the performance of access to the storage device from other data processing devices; Our goal is to provide the following.

Another object of the present invention is to provide a data processing system as described above, in which a storage word width accessed by a predetermined data processing device among a plurality of data processing devices in one write access is provided. The object of the present invention is to provide a means by which it is possible to rewrite only the contents of any part of the bit fields. According to the present invention, in a data processing system including a storage device and a plurality of data processing devices that access the storage device, a storage area of the storage device is accessed from the plurality of data processing devices. Means for providing a shared storage area for storing a shared storage word, configuring the shared storage word by dividing it into a plurality of fields, and setting field specification information consisting of a bit string for each divided field of the shared storage word. a means for detecting a write request to the storage device from a specific data processing device among the plurality of data processing devices; and a means for detecting the write request and accessing the storage device. and the write access allows a portion of the data specified to be written in the storage device to be accessed by the specific data processing device to write a portion corresponding to the specified field according to the set field specification information. A memory access method may be provided that can rewrite a corresponding portion of write data input from the storage device and store it in the storage device.

Next, the present invention will be explained with reference to the drawings.

Referring to FIG. 1, a general configuration example of a data processing system obtained using the present invention is shown. 102-1
102-3 are data processing devices that execute data processing independently of each other, and exchange information with each other via the storage device 101.

101 is a plurality of data processing devices 102-1 to 102-
It is a storage device shared by 3.

100 is a storage control device which is the main object of the present invention, and the storage device 101 is connected to a plurality of data processing devices 102-1 to 102-10.
2-3 in a time-divisional manner.

Referring to FIG. 2, a block diagram of a communication control device that is a specific embodiment of the present invention is shown.

204-1 to 204-3 indicate lines accommodated in this communication control device.

Reference numeral 202-1 is a line scanning unit that scans the accommodation lines 204-1 to 206-3 at regular intervals to generate and disassemble transmit and receive bits, and assemble and disassemble transmit and receive characters.

202-2 identifies the transmitted and received characters assembled and disassembled by the line scanning unit 202-1, and performs error detection processing, error detection addition processing, and error detection character addition processing in accordance with a predetermined transmission control procedure. , is a character processing unit that controls the transfer of transmitted and received characters via the interface 205 with the central processing unit to which this communication control device is connected.

Since the character processing section 202-2 has different control and character processing methods depending on the transmission control procedure handled, it is usually program-controlled to provide flexibility. A program storage device 203 stores a program for controlling the character processing section 202-2, and is used for reading only.

201 is a storage device used by the line scanning section 202-1 and the character processing section 202-2 in a time-sharing manner, and a part of the storage area is used as a communication area by the line scanning section 202-2.
02-1 and the character processing section, and is used for exchanging data and control information between the line scanning section and the character processing section.

Reference numeral 200 denotes a storage control section for controlling the storage device 201 to be used in a temporally divided manner by the line scanning section 202-1 and the character processing section 202-2.

Referring to FIG. 3, an example of a data structure of a storage word stored in the communication area in the storage device 201 is shown.

300 is a storage word (hereinafter referred to as line scan word)
The bit division within the line scan word 300 is 30.
1 to 306.

The line scan word 300 exists corresponding to each of the communication lines 204-1 to 204-3 accommodated in this communication control device. A flag section 301 is a bit field for indicating that there is a processing request from the line scanning section 202-1 to the character processing section 202-2.

Reference numeral 302 is a bit field in the order section for defining the operation of the line scanning section 202-1.

For example, if a command issued from the central processing unit via the interface 205 in response to a certain line is a reading command, the line scanning unit 202-1 operates to read data from that line. Character processing section 202-2
is the order part 30 of the line scan word 300 corresponding to the line.
Set the content of 2 to "read". If the command is "send command" which instructs to send data to the line, the content of the order section 302 becomes "send". Monitor other line statuses. There are orders to control the state of the line, orders to control the state of the line, etc., but since they do not affect the nature of the present invention, the details are omitted. 303 is a bit field for storing transmitted and received characters. This is the buffer section.

This character buffer section 303 is used for exchanging transmitted and received characters between the line scanning section 202-1 and the character processing section 202-2. 304 is the line scanning unit 2
02-1 is used in 7 to assemble serial signals from the line into parallel signals or to decompose parallel signals into serial signals according to the contents shown in the order part 302 of the line scan word 300. This is a serial/parallel conversion buffer section in a bit field.

Reference numeral 305 is a bit field for a character synchronization counter used to control the serial/parallel conversion of transmitted and received characters by the line scanning section using the serial/parallel conversion buffer section 304.

306 is a line scanning unit 202-1 that samples data bits from the line, determines the median value, generates received bits, decomposes transmitted data bits, and controls the bit length. This is a bit field for the bit synchronization counter used.

Referring to FIG. 4, the memory cycle relationship is shown when the line scanning section 202-1 and character processing section 202-2 in this communication control device share the storage device 201.

A line 400 is a time diagram showing the memory cycle of the storage device 201, where T is the access time allocated to the line scanning section 202-1 and Ts is the access time allocated to the character processing section 202-2. TM is the line scanning period. R is the read time of the storage device 201, and W is the write time of the storage device 201. L is the logical time used by the line scanning section 202-1. Line 401 shows the address information of each memo cycle for storage device 201. N,. n+1 is address information P.n+1 when accessed by the line scanning unit 202-1 corresponding to the access time Ts on the line 400. ．． q
is the address information when accessed by the character processing section 202-2 corresponding to the access time Tp at 400. The operation of the line scanning section 202-1 at the access time T on the time diagram 400 will be explained.

The line scanning unit 202-1 accesses the storage location in the storage device 201 where the line scan word 300 of the line to be scanned is stored, reads out the line scan word from the storage device 201 for a reading time R, and scans the line. The operation specified by the contents displayed in the order section 302 in the word 300 is performed within the logical time L, and the line scan word 300 is stored in the storage location again after a writing time W. storage device 20
Complete one access to 1. As a result of this operation, the flag bit section 301, character buffer section 303, serial/parallel conversion buffer section 30, character synchronization counter section 305, bit synchronization counter section 306, etc. of the line scan word 300 are rewritten as necessary. Restored. For example, when the order section is for "reading" or "sending", the contents of the bit synchronization counter section 306 are incremented by 1 in order to generate received bits and decompose transmitted bits. Bit synchronization counter section 30
If the contents of 6 indicate completion of bit generation and completion of bit decomposition, 1 is added to the contents of the character synchronization counter section 305, and when reception of one character is completed, the received character is stored in the character buffer section 303. is displayed, sets a flag in the flag bit section 301, and requests the character processing section 202-2 to take over the received character. When the transmission of one character is completed, the character is stored in the character buffer section 303. Processing section 20
The transmission character already given by 2-2 is transferred to the serial/parallel conversion buffer section 304, and the decomposition and transmission of the next transmission character is started.A flag is also set in the flag bit section 301, and the character processing section 202-2
It also requests the character buffer unit 303 to prepare the next transmission character. On the other hand, the character processing section 202-2 accesses the storage device 201 using the access time Tp assigned to the character processing section 202-2 of the storage device 201 in the time diagram 400. 2 is program-controlled, so that only one of "reading" and "゜writing" operations is performed in one access time Tp. Also, unlike the line scanning unit 202-1, all access times T
, there is no access operation, and the access time T is changed only when it is necessary for program control.
, to access the storage device 201. The character processing unit 202-2 searches for a line scan word with a flag set in the flag bit unit 301, and when detected, performs processing according to the state of the line at that time, and then
The flag set in the flag bit section 301 by the line scanning section 201-1 is reset. Furthermore, the character processing section 202-2 can also access the line scan word 300 for which no flag is set in the flag bit section 301 and perform necessary processing. According to the above explanation, the line scanning section 202-1 and the character processing section 202-2
This means that the storage device 201 is accessed using the access time allocated to each processing unit of the storage device, regardless of whether the storage device 201 is accessed by the other party, and that each processing unit It can be seen that the address at which each processor accesses the storage device 201 is determined solely by the convenience of each processing unit, regardless of the address at which the other party accesses it.

Line scan word 30 from character processing unit 202-2 for a mechanism for partially writing to a storage device in such a device.
Let us explain a partial write operation to 0 as an example. Fifth
Referring to the figure, detailed interfaces between the character processing section 202-2, the storage control section 200, and the storage control section 200 and the storage device 201 are described. In Figure 5,
200 is a storage control unit; 201 is a storage device; 302-1 is a line scanning unit; 202-2 is a character processing unit;
In the figure, these are the same as those shown as 200, 201, 202-1, 202-2, respectively. At the interface between the storage control unit 200 and the storage device 201, 50
1 sends a signal instructing execution of access to the storage control unit 200.
Conductive wires for leading from to the storage device 201, 502-1 to 502-5
02-2 is a conductor line for guiding address information from the storage control unit 200 to the storage device 201, and 503-1 to 503-2 are conductive lines for guiding output information from the storage device 201, that is, read data to the storage control unit 200. Conductor for, 504-1
504-2 is a conductor for guiding output information from the storage control unit 200, that is, write data, to the storage device 201. Character processing section 202-2 and storage control section 200
In the interface, 521 is the character processing section 2.
Conductive wires 522-1 to 522-2 are for guiding a signal indicating that there is an access request to the storage device 201 from 02-2 to the storage control unit 200. Conductive wires for guiding from -2 to storage control unit 200, 523-1 to 5
23-2 is a conductor for guiding read data from the storage device 201 in response to read access from the character processing device from the storage control unit 200 to the character processing unit 202-2; 524-1 to 524-2 are character processing lines; storage device 20 upon write access from section 202-2.
A conducting wire 525 is a conducting wire 5 for guiding data written to 1 from the character processing section 202-2 to the storage control section 200.
21, the character processing unit sends a signal indicating that the requested access to the storage device 201 is a read access;
A conductive wire for leading from 202-2 to storage control unit 200, 5
26 is a conductor 521 for guiding a signal indicating that the requested access to the storage device 201 is a write access from the character processing unit 202-2 to the storage control unit 200; 527-1 is a character requested by the conductor 521; The storage control unit 200 informs the character processing unit 202 that an access request to the storage device from the processing unit has been detected.
-2, the access to the storage device 201 from the character processing device 202-2 requested by the conductor 521 is executed, and if the access is a read access, the access to the storage device 201 is executed. Indicates that data is prepared on conductors 523-1 to 523-2,
For write access, conductors 524-1 to 524-
2 Conductive wires 528-1 to 528- for guiding a signal indicating that writing of the write data led to the storage control unit 200 to the designated storage position is completed to the character processing unit 202-2. 2 leads information of 1 or O (hereinafter referred to as a mask pattern) from the character processing unit 202-2 to the storage control unit 200, corresponding to each bit constituting the storage word stored in the storage device 201. A conductive wire 529 is a conductive wire for guiding a signal from the character processing section 202-2 to the storage control section for instructing to take out the mask patterns prepared on the conductive wires 528-1 to 528-2. Incidentally, when the scanning control unit 201-1 accesses the storage device 201, the above-mentioned line scanning word 300
゜゜reading゜゜processing゛゜“restoring” is executed within one allocated memory cycle,
There is no need to provide a partial write function for the line scanning section 202-1 in the storage control section, and therefore, the detailed interface between the line scanning section 202-1 and the storage control section 200 is omitted in FIG. Referring to FIG. 6, storage control section 20
A detailed illustrative configuration of the present invention in No. 0 is described.

In Figure 6, 501,502-1 to 502-2,50
3-1 to 503-2 and 504-1 to 504-2 have already been shown in FIG. 5 as interface lines between the storage control section 200 and the storage device 201. Similarly, 521,5
22-1~522-2,523-1~523-2,52
4-1 to 524-2, 525, 526, 527-1, 5
27-2, 528-1 to 528-2, 529 are interface lines between the character processing section 20J2-2 and the storage control section 200. 612-1 to 612-2 are conducting wires for carrying address information from the line scanning section 202-1; 613-
1 to 613-2 are conductive wires 614-1 to 61 for carrying read data from the storage device to the line scanning unit 202-1.
4-2 is a conductor for carrying write data from the line scanning section 202-1 to the storage device 201.

600 is a line scanning unit 202 for the storage device 201.
-1 and the character processing unit 202-2 in a time-divisional manner, and in particular, the part that controls the access from the character processing unit 202-2 is described in detail.

Reference numeral 601 denotes a circuit block for creating various control signals necessary for operating the storage controller as intended, and some of the created control signals are connected to the conductor 6.
02 to 605.

Referring to FIG. 7, time diagrams 702-713 are used to explain the operation of the detailed description of the invention set forth in FIG.
is listed. The operation of the circuit shown in FIG. 6 will be explained with reference to FIG. Lines 702, 703, 704,
705 is a time diagram of the signal levels on conductors 602, 603, 604, and 605, respectively. The signals shown in the time diagrams 702 and 703 are used to allocate the memory cycles of the storage device to the line scanning section 202-1 and the character processing section 202-2, as already shown in the time diagram 400 of FIG. While the signal on the conductor 602 is at the 1 level (indicated by Ts on the time diagram 702), the signal on the conductor 603 from the line scanning unit 202-1 is at the 1 level.
While at the level (indicated by Tp on the time diagram 703), the character processing unit 202-2 is controlled to execute access. The conducting wires 602 and 603 are never at the 1 level at the same time, and when one is at the 1 level, the other is at the O level, and this is repeated at the line scanning period TM. The signal shown in the time line diagram 704 is a signal for searching for an access request from the character processing section, and is used immediately when the memory cycle Tp assigned to the character processing section 202-2 is activated. The signal is first input to the gate of a flip-flop 606 via a conductor 604 .
606 indicates that when the interface line 521 leading to the access request from the character processing unit 202-2 is activated as shown in the time line diagram 706 in FIG.
When the access request search pulse is input to the gate, the flip-flop becomes set, and this state is shown in FIG. This is illustrated by diagram 707.

The set side output of the flip-flop 606 is the gate 607.
through the interface line 527-1, and notifies the character processing unit 202-2 that an access request has been detected. Character processing section is interface line 5
27-1 is activated, the interface line 521 is activated and the access request continues;
When the interface 527-1 becomes active, the interface line 521 ceases to be active. The arrow marked C in FIG. 7 shows this situation. On the other hand, if the flip-flop 606 is in the set state, the seventh
As shown in the time diagram 708 in the figure, the AND circuit 608 is activated only during the memory cycle Tp when the conductor 603 is in the 1 state, and makes the conductors 610-1 and 610-2 active. is not in the set state, the AND circuit 608 is not activated even if the signal on the conductor 603 becomes 1 level, and therefore the memory cycle TP
However, conductors 610-1 and 610-2 are not activated.

The output of the AND circuit 608 passes through the OR circuit 609 to enable the interface line 501 for accessing the storage device 201, so that the storage device 201 is accessed. Also, since conductor 610-1 is active, interface line 502-1 for sending address information to storage device 201 by address selection circuit 620 is connected.
~502-2 are interface lines 522-1~522-5 for receiving address information from the character processing section 202-2.
22-2. The conductor 611 is the memory cycle T
It is activated in response to memory cycle Tp
It will not be activated in If conductor 611 is activated, interface wires 502-1 to 502
-2 is connected to interface lines 612-1 to 612-2 for receiving address information from line scanning section 202-1. When the storage device 201 is accessed, the storage words stored in the storage locations indicated by the interface lines 502-1 to 502-2 pass through the storage words for a time indicated by R in FIG. 503-1~50
Output on 3-2. This output information is held until the next access to storage device 201 is made.
A time diagram 709 in FIG. 7 shows this situation. Since the conducting wire 610-1 is in the active state, the AND gate circuits 623-5 to 623-6 are in a conductive state,
Read data on interface lines 503-1-503-2 appears on conductors 623-3-623-4. On the other hand, since the conducting wire 611 is not in an active state, the AND gate circuits 613-5 to 613-6 are in a non-conductive state, and therefore the interface lines 613-1 to 613-6 for carrying read data to the line scanning section 202-1 are in a non-conductive state. 2, the information on the interface lines 503-1 to 503-2 is not output. With interface line 525 active as shown in time diagram 710 of FIG. 7, if the access from character processor 202-2 is to read a stored word, the AND Gate circuit 623
-7 to 623-8 become conductive, and the read data in the time diagram 709 is transferred to the interface lines 523-1 to 523-.
2 to the character processing section 202-2, and the signal on the interface line 525 is sent to the OR circuit 62.
Conductor wires 625-1 to 625- through 4-1 to 624-2
2 and connects the storage word configuration circuit 630 to conductor 6.
27-1 to 627-2 are connected to conducting wires 623-3 to 623-4. On the other hand, since interface line 526 and interface line 525 are not activated at the same time,
During a read access in which interface line 525 is active, interface line 526 is not activated, and therefore AND circuits 528-1 to 528-2 are inactive, and their output lines 626- 1~626-
2 is also enabled, via storage word configuration circuit 630, to conductors 627-1 to 627-2 and interface line 52.
4-1 to 524-2 are never connected. Further, since conductor 610-1 is activated as shown in time diagram 708, interface lines 504-1 to 504-2 and conductors for conveying stored data to storage device 201 via stored data selection circuit 640 are connected. 627-1~627-
2 are connected, and eventually the interface lines 504-1 to 504-1 are connected to
On 504-2, interface lines 503-1 to 50
The exact same information that was output on 3-2 is displayed. The information on the interface lines 504-1 to 504-2 is transferred to the storage device 2 over a period of time indicated by W in the time diagram 711.
01 interface lines 502-1 to 502-2, and one read access to the storage device 201 is completed. Note that the interface wire 525 is also connected to the conductive wire 610 as shown in the time diagram 710.
-2 is activated as shown in the time diagram 708, so when the signal shown in the time diagram 705 is input from the conductor 605, the AND circuit 629 is activated as shown in the time diagram 712. , the output signal passes through the OR circuit 631, activates the interface line 527-2, and connects the interface line 523-2 to the character processing section 202-2.
1 to 523-2 are notified that the read data is prepared. Arrows D, e, and f in FIG. 7 show how the AND circuit 629 is activated. Detecting the access request from the character processing unit 20-2, time line diagram 7
The flip-flop 606 in the set state as shown in FIG.
When the signal above 0-2 is input, the output conductor of the delay gate pulse generation circuit 632 that outputs the signal shown in the time diagram 713 is introduced into the reset gate R, so the signal shown by q in FIG. It will be reset as shown by the arrow. The character processing unit 202-2 connects the interface line 527-1
By detecting the transition from the active state to the inactive state, it knows that the access to the storage device 201 is complete and ceases to continue the interface line 525 in the active state. This situation is shown by arrow k in FIG. Next, the operation of the circuit shown in FIG. 6 will be explained in the case of write access from the character processing section 202-2.

650 is a circuit for displaying bit field information of the storage word, and flip-flop circuits 651-1 to 651- correspond to each bit constituting the storage word.
2.

The character processing section 202-2 is connected to the interface line 52.
9 by activating interface line 528.
A mask pattern can be freely set in this register circuit 650 via -1 to 528-2. In this embodiment, before the write access from the character processing unit 202-2, the character processing unit 202-2
It is assumed that the mask pattern from 2 has been set. Each flip-flop 651 of the register circuit 650
-1 to 651-2 are the states of the character processing unit 202-
When executing a write access to the storage device 201 from No. 2, it is displayed whether the bit position of the storage word corresponding to the flip-flop is to be rewritten or not, and the reset state is "Rewrite" and the set state is "Rewrite". “Do not rewrite” is supported. For a write access from character processor 202-2, interface line 526 is activated as shown in time diagram 710, and interface line 525 is not activated.
Therefore, OR circuit 624-1 corresponds to time diagram 710.
624-2, those in which the corresponding flip-flops of the register circuits 650 are in the set state are in the active state, and those in the reset state are in the inactive state. Further, the AND circuits 628-1 to 628-2 are connected to the register circuit 65, respectively.
If the flip-flop corresponding to 0 is in the set state, it becomes inactive, and if it is in reset state, it becomes active. Therefore, during a write access from the character processing unit, the OR circuit 624 and the AND circuit 628 corresponding to the same flip-flop of the register circuit 650 are not activated at the same time, and the OR circuit 624 and the AND circuit 628 corresponding to the same flip-flop of the register circuit 650 are not activated at the same time. The output conductors 625-1 to 625-2 of the OR circuits 624-1 to 624-2 and the AND circuit 628-
Among the output conductors 1 to 628-2, only one becomes active. Thus, storage word configuration circuit 630
, whose output conductors 627-1 to 627-2 are connected to flip-flops 6 corresponding to each bit making up the storage word.
Depending on the state of 51-1 to 651-2, it may be connected to interface lines 524-1 to 524-2 for guiding write data from the character processing device, or
09, it is determined whether to connect to conductive wires 623 to 623-4 for leading read data. More specifically, among the output conductors 627-1 to 627-2, the flip-flops 651-1 to 651 constituting the register circuit 650 are connected through the storage word configuration circuit.
-2, those corresponding to the flip-flops in the set state are connected to the corresponding conductors 623-3 to 623-4, and those corresponding to the flip-flops in the reset state are connected to the interface lines 524-1 to 524-2. are connected to their respective corresponding ones. If the access is from the character processing unit, the conductor 610-1 is activated as shown in the time diagram 708, so the interface lines 504-1 to 504- for carrying stored data to the storage device 201 are activated.
2 is connected to the conductors 627-1 to 627-2, and based on the information displayed in the register circuit 650, the read data appearing on the interface lines 503-1 to 503-2 and the interface lines 524-1 to 524- 2 and the write data appearing on the storage word configuration circuit 6.
The storage words configured by 30 are shown in the time diagram 711
It takes a time indicated by W to be stored in the storage device 201. Note that in write access from the character processing unit 202-2, the interface line 526 is activated as shown in the time line diagram 710, and the conductor line 610-2 is activated as shown in the time line diagram 708, so the AND circuit 633 is activated. The delay gate pulse generating circuit 634 activates the conductor 635 at a time position as shown in the time diagram 712-2. The signal on lead 635 passes through OR gate 631 to enable interface line 527-2, informing the character processing device that the write access is complete. After the access is complete, flip-flop 606 is reset and interface line 526 transitions to an inactive state as shown in time diagram 710, similar to the read access. In this embodiment, by introducing the conductive wire 635 into each reset gate of all the flip-flops 651-1 to 651-2 constituting the register circuit 650, one-time operation from the character processing section 202-2 Each time a write access is completed, all flip-flops 651-1 to 65 of register circuit 650 are
1-2 is in the reset state. By doing this, the next time the character processing unit 202-2 writes to the storage device, all bits of the storage word will be in a "rewrite" state. In the device, the storage area other than the communication area of the storage device 201 is used only by the character processing unit 202-2.
When writing access to that area, all bits of the storage word are often rewritten, and moreover,
Due to character processing, after accessing the communication area once, accessing storage areas other than the communication area is far more likely than accessing the communication area continuously. Even if access were to be made, it is highly unlikely that a portion of the register circuit 650 would be written twice using the same mask pattern.
It is better to keep all the bits of the stored word in the "゜rewrite" state each time one write access is completed, so that the next time you perform an access to rewrite all the bits of the stored word. In this case, there is no need to perform the operation of setting a mask pattern in the register circuit 650, and the number of plastics can be saved, especially when the character processing section is controlled by a program as in this embodiment.
Note that at cycle time Ts, the conducting wire 611 is activated and access from the line scanning section 202-1 is performed. FIG. 8 shows, as an example, a case in which the function of partially writing a stored word from the character processing section of the present invention is most effective, and shows the line scanning section 202-1 and the character processing section 202-1 in the embodiment. 2 schematically shows how information is exchanged with the line scan word 300. 801-0 represents the entire storage area of the storage device 201, 80
1-1 indicates a communication area, and 801-2 indicates a storage position of a line scan word corresponding to the n-th line.

802-1 indicates that processing is performed by the line scanning unit 202-1.

802-2 indicates that processing is performed by the character processing unit 202-1.

A line 810 indicates a memory cycle of the storage device 201 corresponding to the time diagram 400 of FIG. 4, Tp-1 and Tp-3 are memory cycles assigned to the character processing unit 202-2, -2 is line scanning section 202-1
represents the memory cycles allocated to line 8
11 indicates in parentheses the address information for the storage device 201 in each memory cycle corresponding to the storage device 201 in correspondence with the diagram 401 in FIG. 4, and the character processing unit 202-2
If the access is from the line scanning unit 202-1, the subscript P is added, and if the access is from the line scanning unit 202-1, the subscript S is added outside the parentheses. Further, referring to FIG. 9, a specific example of a line scanning word and a mask pattern is described for explaining the schematic diagram of FIG. 8.

With reference to FIG. 9, how the partial write operation is effectively performed in FIG. 8 will be explained. Now, using the cycle time Tp-1, the character processing unit reads out the line scan word LSWn-10 corresponding to the n-th accommodated line from the storage position indicated by 801-2 of the storage device 201, and performs processing 802-2. If the processed result line scan word LSWn-40 is to be stored again in the storage location 80, 1-2 of the storage device 201 using the cycle time Tp-3, then the cycle time Ts- 2 exists at the time position shown in the time diagram 810, and in order for the line scanning unit 202-1 to scan the n-th accommodated line using this cycle time T,-2, the storage device 201 The line scan word LSWn-20 corresponding to the n-th accommodated line is read from position 801-2 and processed by processing 802-1. Assume that an event occurs that causes Wn-21 to be stored again in storage location 801-2 of storage device 201 within cycle time T,-2.

It is assumed that LSWn-10 has the content shown at 910 in FIG. Since T2-1 is a read access from the character processing unit 202-1, the LSW
Even if the line scan word LSWn-11 having exactly the same content as n-10 takes a writing time W within the cycle time Tp-1, it is stored again in the original storage location 801-2. Therefore,
The line scanning unit 202-1 reads at cycle time Ts-2? The contents of Wn-20 are also the same as shown in 910. The bit field 912 in 910 is
Bit field 302 within line scan word 300 of FIG.
This corresponds to the order part, and the information in binary representation of "1,0" means "° delivery."

The line scanning unit 202-1 performs various processing operations prescribed in accordance with the sending order, but the processing 802-1 for the line scanning word is performed using the bit synchronization counter field corresponding to 306 in FIG. This is to increment the contents of bit synchronization counter field 916 by 1.
30 in Figure 3.
Character synchronization counter field 91 corresponding to 5
This is to add 1 to the contents of 5. In the communication control device of the embodiment, the transmitted bits are decomposed by bit sampling 11 times, so the bit synchronization counter is 11 times.
controlled by Therefore, if LSWn-20 is as shown at 910, the line scan word LSWn-21 resulting from processing 802-1 will be as shown at 920. LSWn-21 takes a writing time W within cycle time T,-2 to write to the storage location 801 of the storage device 201.
-2. On the other hand, the character processing section 202-2
The line scan word LSWn with the content as indicated by 910 in
Processing 802-2 for -10 provides the next transmission character to the character buffer section 913 corresponding to 303 in FIG.
11 flags are reset. Therefore, processing 8
The line scan word LSWn-40 as a result of performing 02-2 is 9.
30. However, the line scanning section 202
-1 and the character processing unit 202-2 independently execute data processing, and the character processing unit 202-2 uses the line scanning unit to scan the line scanning word for the n-th accommodated line at cycle time Ts-2. It is not detected that processing such as 802-1 has been performed on. Therefore, before the character processing unit 202-2 accesses the storage device 201 to store LSWn-40, the storage control unit 200
9 on the register circuit 650 described in FIG.
If the information indicated by 50 is set and then a write access is performed using the cycle time Tp-3, the access requires a read time R of the cycle time Tp-3, Line scan word LSWn-30 with the same content as LSWn-21 read from storage location 801-2, ie, the content shown at 920 in FIG.
and the line scan word ? as a result of processing 802-2 performed by the character processing unit. Wn-41, storage control unit 20 according to mask pattern MSK indicated by 950.
Processing 80 by the storage word configuration circuit 630 provided in 0
3 is performed, a new line scan word 1-SWn-31 with contents as shown at 940 in FIG. The data is stored in storage location 801-2, and thus information is successfully exchanged between character processing section 202-2 and line scanning section 202-1. As explained above, the present invention provides a means for setting field specification information consisting of a string of bits provided corresponding to each divided field in a shared storage word in a shared storage area, and a method for accessing the shared storage area. and a means for identifying that the write access is from a specific data processing device among the plurality of data processing devices, and from the specific data processing device to the storage device including the above-mentioned shared storage area as a storage area. When writing data, data is rewritten in the field specified by the set field specification information from the specific data processing device to the storage device.
A storage device having a shared storage area that can be accessed once and accessed by a plurality of data processing systems is provided, and multiple data processings can be performed via a shared storage word stored in the shared storage area. This has the effect of efficiently realizing a data processing system that can exchange information between systems.

That is, in a data processing system such as the one described above, each data processing device can influence the field of a shared storage word that can be rewritten by accessing the storage device from another data processing device. Without,
purpose. Since it is possible to specify and rewrite only specific fields, each data processing device that accesses the storage device can be When the data processing device needs to access the storage device, it can be accessed quickly.

[Brief explanation of the drawing]

] FIG. 1 is a block diagram of a data processing system, FIG. 2 is an overall block diagram of a communication control device according to an embodiment of the present invention, FIG. 3 is a bit structure diagram of a line scanning word, and FIG. 4 is a block diagram of an implementation of the present invention. FIG. 5 is a detailed diagram of the interface between the character processing unit and the storage device in the communication control device according to the embodiment of the present invention; FIG. 6 is a detailed circuit diagram of the storage control section according to the embodiment of the present invention, FIG. 7 is a time diagram for explaining the operation of the storage control section according to the embodiment of the present invention, and FIG. 8 is a detailed circuit diagram of the storage control section according to the embodiment of the present invention. FIG. 9 is a schematic diagram showing how information is exchanged between the character processing section and the line scanning section in the communication control device according to the embodiment of the present invention. FIG. 4 is a concrete diagram of line scanning words exchanged with a scanning unit. 100...Storage control device, 101...
Storage device, 102-1 to 102-3... Data processing device, 200... Storage control unit, 201...
...Storage device, 202-1...Line scanning unit, 202-2...Character processing unit, 203...
...Program storage device, 204-1 to 204-3
...Line, 205...Interface.

Claims (1)

[Claims] 1. In a data processing system including a storage device and a plurality of data processing devices that access the storage device, a shared storage word accessed by the plurality of data processing devices is stored in a storage area of the storage device. a means for setting field specification information consisting of a bit string corresponding to each divided field of the shared storage word; comprising means for detecting a write access request to the storage device from a specific data processing device among a plurality of data processing devices; and means for detecting the write access request and accessing the storage device; In the write access, a part of the data stored in the storage location specified for writing in the storage device, which corresponds to the field specified by the set field specification information, is transferred to the specified data. A memory access method characterized in that write data input from a processing device is rewritten with a corresponding portion and stored in the storage device.