JPS6041262A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6041262A
JPS6041262A JP14874683A JP14874683A JPS6041262A JP S6041262 A JPS6041262 A JP S6041262A JP 14874683 A JP14874683 A JP 14874683A JP 14874683 A JP14874683 A JP 14874683A JP S6041262 A JPS6041262 A JP S6041262A
Authority
JP
Japan
Prior art keywords
electrons
layer
light
resistance state
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14874683A
Other languages
Japanese (ja)
Inventor
Haruhisa Kinoshita
木下 治久
Seiji Nishi
清次 西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP14874683A priority Critical patent/JPS6041262A/en
Publication of JPS6041262A publication Critical patent/JPS6041262A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/802Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors
    • H01L29/803Programmable transistors, e.g. with charge-trapping quantum well

Abstract

PURPOSE:To increase the storing time and to enhance the integrating density by controlling the flow rate of secondary electrons formed in a hetero junction multilayer film by the space charge amount of the electrons collected to an electron trap and the light emitting effect. CONSTITUTION:In a semiconductor having a semi-insulating GaAs substrate 11, non impurity-added GaAs layer 12, 16, impurity-added AlGaAs layers 13, 15, Si-high density N type AlGaAs layer 14, a voltage is applied between a source electrode 17 and a drain electrode 18, hot electrons in a channel 19 are applied into the layer 14, collected to the high density electron trap to high resistance state. After the voltage between the source and the drain is set to zero for several minutes, the voltage is again applied. Then, it becomes high resistance state. When a light is emitted in this state, the electrons collected to the trap are flowed to the channel 19, becoming low resistance state, thereby maintaining the low resistance state even if the light emission is stopped.

Description

【発明の詳細な説明】 (技術分野) 本発明は2次元状態に分布する高移動度の電子の流量を
光によって制御する半導体装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor device in which the flow rate of high-mobility electrons distributed in a two-dimensional state is controlled by light.

(従来技術) 伝導電子の流量を光によって制御する従来の半導体装置
の構造図を第1図に示す。第1図において、1はB(ボ
ロン)をドープしたp型Siのエミッタ、2はAs (
ヒ素)をドープしたn型Stのペース、3はBをドープ
したp型Siのコレクタである。
(Prior Art) FIG. 1 shows a structural diagram of a conventional semiconductor device in which the flow rate of conduction electrons is controlled by light. In Fig. 1, 1 is a p-type Si emitter doped with B (boron), and 2 is an As (
3 is a p-type Si collector doped with B.

エミッタとベースの接合近傍に光を照射することによシ
ミ子・正孔対が形成され、ベース領域に少数キャリアの
注入が行なかれて光の照射量にほぼ比例したコレクタ電
流が流れる。第1図に示した半導体装置の光照射量に対
する電気的特性の変化が第2図に示しである。電流・電
圧特性は5極管特性を示し光の照射量に比例したコレク
タ電流が流れる。従ってこの半導体装置は光の照射量を
変化させると同時にコレクタ電流も変化するので過去に
照射された光の照射量に関する記憶作用がな ・い。又
このような構造の半導体装置は一枚の基板上に多数集積
化するのが難しく、ゾレーナ型の集積回路に応用するこ
とが困難であるという欠点があった。
By irradiating the vicinity of the emitter-base junction with light, shim-hole pairs are formed, minority carriers are injected into the base region, and a collector current approximately proportional to the amount of light irradiation flows. FIG. 2 shows changes in the electrical characteristics of the semiconductor device shown in FIG. 1 with respect to the amount of light irradiation. The current/voltage characteristics are pentode characteristics, and a collector current proportional to the amount of light irradiation flows. Therefore, in this semiconductor device, since the collector current changes at the same time as the amount of light irradiation changes, there is no memory function regarding the amount of light irradiated in the past. Furthermore, it is difficult to integrate a large number of semiconductor devices having such a structure on one substrate, and it is difficult to apply them to a Zollena type integrated circuit.

(発明の目的) この発明の目的はこれらの欠点を解決するため。(Purpose of the invention) The purpose of this invention is to overcome these drawbacks.

光の照射量に応じた空間電荷の蓄積量を制御可能にし、
過去の光照射の有無の記憶作用をもつ半導体装置を提供
するにある。
It is possible to control the amount of space charge accumulated according to the amount of light irradiation,
It is an object of the present invention to provide a semiconductor device having a memory function of the presence or absence of past light irradiation.

(発明の構成) この発明は上記目的を達成するために、電子トラップ密
度が大きく電子親和力が相対的に小さいn又はn千手導
体層と、電子トラップ密度が小さくかつ不純物密度が充
分少なく電子親和力が相対的に大きい半導体層とのへテ
ロ接合構造をもうけ、電子親和力が相対的に大きい半導
体層側のへテロ接合界面に2次元電子を蓄積してチャン
ネル層を作シ、電子親和力が相対的に小さい半導体層中
に伝導電子を注入し電子トラップに捕獲させることによ
シ負の空間電荷領域を形成してチャンネル層を高抵抗化
し、光を照射することによシ捕獲された電子を放出させ
てチャンネル層内に2次元電子を蓄積させ低抵抗化させ
るようにしたものであり、以下実施例について説明する
(Structure of the Invention) In order to achieve the above object, the present invention provides an n or n thousand-handed conductor layer with a large electron trap density and a relatively low electron affinity; creates a heterojunction structure with a relatively large semiconductor layer, and creates a channel layer by accumulating two-dimensional electrons at the heterojunction interface on the side of the semiconductor layer that has a relatively large electron affinity. By injecting conduction electrons into a small semiconductor layer and trapping them in an electron trap, a negative space charge region is formed to make the channel layer highly resistive, and the trapped electrons are released by irradiation with light. In this embodiment, two-dimensional electrons are accumulated in the channel layer to lower the resistance. Examples will be described below.

(実施例) 第3図は本発明の第1の実施例であって、11は半絶縁
GaAs基板、12は不純物無添加の約1000Xの厚
さのGaAs層、13は不純物無添加の約1000Xの
厚さのAAo、3Gaq、7AS層、14は81を高濃
度に添加した約500Xの厚さのN−A70+3Ga0
7As層、15は不純物無添加の約60Xの厚さのAj
?0.3Gao7AS層、16は不純物無添加αaAs
層、17と18はGaAs層16に空けられた穴の中に
埋め込まれた約10μmの間隔をなすAu−Ge /N
i /Auオーミック接合のソース電極とドレイン電極
である。19はGaAs層16の接合界面近傍に蓄積さ
れた2次元電子ガスからなるチャンネルである。これを
動作させるには半導体装置を77°に程度に冷却し、ソ
ース電極17とドレイン電極18との間に約5■の電圧
を印加しチャンネル19内に大きな運動エネルギーをも
った電子(ホットエレクトロン)を流し、このホットエ
レクトロンをSi添加A/ o、3Gao、7AS層1
4内に注入させて高い密度の電子トラップに捕獲させ負
の空間電荷を数多く形成し、チャンネル19を空乏化さ
せることによシ第4図に示すように高抵抗状態にするこ
とができる。
(Embodiment) FIG. 3 shows a first embodiment of the present invention, in which 11 is a semi-insulating GaAs substrate, 12 is an impurity-free GaAs layer with a thickness of about 1000X, and 13 is an impurity-free GaAs layer with a thickness of about 1000X. AAo, 3Gaq, 7AS layer with thickness of , 14 is N-A70+3Ga0 with thickness of about 500X with high concentration of 81 doped.
7As layer, 15 is Aj with a thickness of about 60X without addition of impurities
? 0.3 Gao7AS layer, 16 is αaAs with no impurity added
Layers 17 and 18 are Au-Ge/N embedded in holes drilled in GaAs layer 16 with a spacing of approximately 10 μm.
These are the source and drain electrodes of the i/Au ohmic junction. Reference numeral 19 denotes a channel made of two-dimensional electron gas accumulated near the junction interface of the GaAs layer 16. To operate this, the semiconductor device is cooled to about 77°, a voltage of approximately 5 cm is applied between the source electrode 17 and the drain electrode 18, and electrons (hot electrons) with large kinetic energy are generated in the channel 19. ), and the hot electrons are transferred to the Si-added A/o, 3Gao, 7AS layer 1.
By injecting electrons into the channel 19 and trapping them in high-density electron traps to form a large number of negative space charges and depleting the channel 19, a high resistance state can be achieved as shown in FIG.

この状態よシ、ソース電極17とドレイン電極18との
間に印加された電圧を数分間Ovにして再び1vの電圧
を印加すると前の状態とほぼ等しい高抵抗状態を再現す
る。約1vの電圧を印加したまま光を照射するとSt添
加A10,3 Ga(17As層14内の電子トラップ
に捕獲された電子が光のエネルギーをもらってチャンネ
ル19内に流れ出し低抵抗状態となる。この低抵抗状態
においてはソース電極17とドレイン電極18との間の
電圧が1vと低いためチャンネル19内電子の運動エネ
ルギーが低くチャンネル19内から電子が他の層に注入
されることはなく、光の照射を停止しても低抵抗状態を
維持する。このような構造はGaAsとAlo、3G 
a o、7A aの組み合わせを変えても実現でき、−
例としてGaAs/klO,5Gao、7 Asの代わ
シにG a o、47 I n o、53 A s/A
104a ”052”’などがある。
In this state, when the voltage applied between the source electrode 17 and the drain electrode 18 is set to Ov for several minutes and a voltage of 1 V is applied again, a high resistance state almost equal to the previous state is reproduced. When light is irradiated with a voltage of about 1 V applied, electrons captured by electron traps in the St-doped A10,3Ga (17As layer 14) receive energy from the light and flow into the channel 19, resulting in a low resistance state. In the resistance state, the voltage between the source electrode 17 and the drain electrode 18 is as low as 1V, so the kinetic energy of the electrons in the channel 19 is low, and electrons are not injected from the channel 19 into other layers, which prevents light irradiation. maintains a low resistance state even if the
It can be realized by changing the combination of a o, 7A a, -
For example, instead of GaAs/klO, 5Gao, 7As, Gao, 47Ino, 53A s/A
104a "052"' etc.

(5) 以上説明したように、第1の実施例ではGaAsとAA
o、3Ga(1,7ASのへテロ接合多層膜中に形成さ
れたチャンネル19内の高移動度の2次元電子ガスを、
高濃度の電子トラップを含むSt添加Alo。3Gao
。7AS層14中に注入又は捕獲された電子を光照射に
よシ放出することによシチャンネル19の電気伝導度を
変えることができる。いったん捕獲された電子の捕獲の
寿命が数分以上ときわめて長い為、数分以上の寿命をも
つ記憶素子として利用することができる。又この半導体
装置は1枚の基板上に容易に多数個プレーナ構造で製造
することができる為、集積回路に容易に応用できるとい
う利点がある。
(5) As explained above, in the first embodiment, GaAs and AA
o, 3Ga (1,7AS) heterojunction multilayer film with high mobility in the channel 19,
St-doped Alo containing a high concentration of electron traps. 3 Gao
. The electrical conductivity of the channel 19 can be changed by emitting electrons injected or captured into the 7AS layer 14 by irradiation with light. Once an electron is captured, it has an extremely long lifetime of several minutes or more, so it can be used as a memory element with a lifetime of several minutes or more. Further, since this semiconductor device can be easily manufactured in a planar structure in large numbers on one substrate, it has the advantage that it can be easily applied to integrated circuits.

第1の実施例はソース、とドレインの2個のオーミック
電極からなる半導体装置であったが、第3図は3個のオ
ーミック電極からなる第2の実施例の半導体装置であっ
て、11〜16と19は第3図に示したものと同等であ
る。21〜23はGaAs層16に空けられた穴の中に
埋め込まれたそれぞれ約10μmの間隔をなすAu−G
e /Ni /Auオーミック(6) 電極である。第1の実施例では記憶作用を維持する為に
は光の照射と同時にソース・ドレイン間電圧を変化させ
なければならなかったが、第2の実施例では半導体装置
77°Kに冷却して電極21に約6Vの一定電圧を印加
し電極23を接地することによシ、Aの側に光を照射し
た場合電極21と22の間の抵抗値が大巾に減少して電
極22の電位が上昇し、逆にBの側に光を照射した場合
電極22と23の間の抵抗値が大巾に減少して電極22
の電位が下降し、A又はBのどちら側に光が照射された
か検出しかつ数分以上の長時間記憶させておくことが可
能となる。Aに光を照射した後Bに光を照射すると、電
極22に示される電位はBに光を照射した場合の電位を
示しており、AとBの2点光入力フリップフロップ回路
を構成している。第2の実施例ではオーミック電極の数
が3個であったが4個以上でも同様の効果が期待できる
。又本実施例は第1の実施例と同様にGaAs /AA
o、3 Gao7 Asの組み合わせをGaO,7In
O,53As /AA’0.48 In0,52 AS
等とすることができる。
Although the first embodiment was a semiconductor device consisting of two ohmic electrodes, a source and a drain, FIG. 3 shows a semiconductor device of a second embodiment consisting of three ohmic electrodes. 16 and 19 are equivalent to those shown in FIG. 21 to 23 are Au-G layers embedded in holes made in the GaAs layer 16 and spaced apart from each other by about 10 μm.
It is an e/Ni/Au ohmic (6) electrode. In the first embodiment, in order to maintain the memory function, it was necessary to change the source-drain voltage at the same time as the light irradiation, but in the second embodiment, the semiconductor device was cooled to 77°K and the electrodes were cooled to 77°K. By applying a constant voltage of about 6 V to 21 and grounding electrode 23, when the side of A is irradiated with light, the resistance value between electrodes 21 and 22 decreases greatly, and the potential of electrode 22 increases. On the other hand, when light is irradiated to the side of B, the resistance value between electrodes 22 and 23 decreases greatly,
The potential of the light decreases, and it becomes possible to detect which side of A or B is irradiated with light and to store it in memory for a long time, such as several minutes or more. When A is irradiated with light and then B is irradiated with light, the potential shown on the electrode 22 indicates the potential when B is irradiated with light, and A and B constitute a two-point light input flip-flop circuit. There is. In the second embodiment, the number of ohmic electrodes was three, but the same effect can be expected with four or more. Also, in this embodiment, GaAs/AA is used as in the first embodiment.
o, 3 Gao7As combination is GaO,7In
O,53As /AA'0.48 In0,52 AS
etc.

(7) 第1図 第2図 (発明の効果) この発明はへテロ接合多層膜中に形成された2次元電子
の流量を、電子トラップに捕獲された電子の空間電荷量
とその光照射効果により制御する方法よりなっているの
で、記憶時間が長いという利点があシ、高集積化が可能
であるので光集積回路のフリップフロツノ回路又は演算
回路に利用することができる。
(7) Figure 1 Figure 2 (Effects of the Invention) This invention calculates the flow rate of two-dimensional electrons formed in a heterojunction multilayer film by the amount of space charge of electrons captured in an electron trap and the effect of light irradiation. This method has the advantage of long storage time, and can be used for flip-flop circuits or arithmetic circuits of optical integrated circuits, since it can be highly integrated.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の光トランジスタの構造図、第2図はその
電気的特性の光照射効果の説明図、第3図はこの発明の
一実施例の光効果半導体装置の構造図、第4図はその電
気的特性の光照射効果の説明図、第5図はこの発明の他
の実施例の説明図である。 11−・・半絶縁性GaAs基板、l 2− GaAs
層、13 ”・A7o、3Gao、7A8層、74−8
i添加Alo、3Ga 007As層、1 s ・・・
A11.3G& []、zAS層、16− GaAs層
、17・・・ソース電極、18・・・ドレイン電極、1
9・・・チャンネル、21〜23・・・オーミック電極
。 (8) 第3図 げVイソV刀L(V 第5図 手続補正書(醪) 16.、千8・1そ1B 特許庁長官 殿 1、事件の表示 昭和58年 特 許 願第148746号2 発明の名
称 半導体装置 3 補正をする者 事件との関係 特許出願人 任 所(〒105) 東京都港区虎ノ門1丁目7番12
号名称(029) ’a中電気工業I本式会社代表者 
取締役社長橋本南海男 4、代理人 住 所(〒105) 東京都港区虎ノ門1丁目7番12
号334−
FIG. 1 is a structural diagram of a conventional phototransistor, FIG. 2 is an explanatory diagram of the light irradiation effect of its electrical characteristics, FIG. 3 is a structural diagram of a photo-effect semiconductor device according to an embodiment of the present invention, and FIG. 4 is an explanatory diagram of the light irradiation effect on the electrical characteristics, and FIG. 5 is an explanatory diagram of another embodiment of the present invention. 11-...Semi-insulating GaAs substrate, l 2- GaAs
Layer, 13”・A7o, 3Gao, 7A8 layer, 74-8
i-doped Alo, 3Ga007As layer, 1 s...
A11.3G & [], zAS layer, 16- GaAs layer, 17... source electrode, 18... drain electrode, 1
9...channel, 21-23...ohmic electrode. (8) Figure 3 V Iso V Sword L (V Figure 5 Procedural Amendment (Moromi) 16., 188.1 So 1B Director General of the Patent Office 1, Indication of the Case 1982 Patent Application No. 148746 2 Title of the invention Semiconductor device 3 Relationship with the case of the person making the amendment Patent applicant's office (105) 1-7-12 Toranomon, Minato-ku, Tokyo
Name (029) 'A Chuo Electric Industry I Main Type Company Representative
Director and President Nankai Hashimoto 4, Agent address (105) 1-7-12 Toranomon, Minato-ku, Tokyo
No. 334-

Claims (1)

【特許請求の範囲】[Claims] 電子トラップ密度が大きく電子親和力が相対的に小さい
n又は1半導体層と、電子トラップ密度が小さくかつ不
純物密度が充分少なく電子親和力が相対的に大きい半導
体層とのへテロ接合構造をもうけ、電子親和力が相対的
に大きい半導体層側のへテロ接合界面に2次元電子を蓄
積してチャンネル層を作り、電子親和力が相対的に小さ
い半導体層中に伝導電子を注入し電子トラップに捕獲さ
せることによシ負の空間電荷領域を形成してチャ、 ン
ネル層を高抵抗化し、光を照射することによシ捕獲され
た電子を放出させてチャンネル層内に2次元電子を蓄積
させ低抵抗化させることを特徴とする半導体装置。
A heterojunction structure is created between an n or 1 semiconductor layer with a large electron trap density and a relatively small electron affinity, and a semiconductor layer with a small electron trap density and a sufficiently low impurity density and a relatively large electron affinity. By accumulating two-dimensional electrons at the heterojunction interface on the semiconductor layer side where the electron affinity is relatively large to create a channel layer, conduction electrons are injected into the semiconductor layer where the electron affinity is relatively small and captured by electron traps. The channel layer is made to have a high resistance by forming a negative space charge region, and the captured electrons are released by irradiation with light to accumulate two-dimensional electrons in the channel layer, thereby lowering the resistance. A semiconductor device characterized by:
JP14874683A 1983-08-16 1983-08-16 Semiconductor device Pending JPS6041262A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14874683A JPS6041262A (en) 1983-08-16 1983-08-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14874683A JPS6041262A (en) 1983-08-16 1983-08-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6041262A true JPS6041262A (en) 1985-03-04

Family

ID=15459692

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14874683A Pending JPS6041262A (en) 1983-08-16 1983-08-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6041262A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0458212A2 (en) * 1990-05-22 1991-11-27 Nec Corporation High speed non-volatile programmable read only memory device fabricated by using selective doping technology

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5726472A (en) * 1980-07-24 1982-02-12 Fujitsu Ltd Semiconductor device
JPS57147284A (en) * 1981-03-06 1982-09-11 Fujitsu Ltd Semiconductor device
JPS5851573A (en) * 1981-09-22 1983-03-26 Fujitsu Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5726472A (en) * 1980-07-24 1982-02-12 Fujitsu Ltd Semiconductor device
JPS57147284A (en) * 1981-03-06 1982-09-11 Fujitsu Ltd Semiconductor device
JPS5851573A (en) * 1981-09-22 1983-03-26 Fujitsu Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0458212A2 (en) * 1990-05-22 1991-11-27 Nec Corporation High speed non-volatile programmable read only memory device fabricated by using selective doping technology

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