JPS6040706B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a channel stopper region in the width direction of a gate of an insulated gate field effect transistor.

In an integrated circuit device using conventional insulated gate MOS transistors, an insulating isolation region between each element is formed using an impurity diffusion layer of the same type as the substrate and a thick field oxide film, and then the M
The OB type transistor was completed by forming a gate insulating film and a gate electrode of polycrystalline silicon in the gate region, and diffusing impurities of the opposite type to the substrate to form the source and drain.

The method for forming this gate electrode is, for example, by forming polycrystalline silicon by vapor phase growth and selectively removing it by photolithography using a photoresist. At the time of photolithography, the gate electrode must completely cover the gate insulating film to allow for manufacturing margins, so the gate electrode always needs to have an overlapping portion on the field oxide film. FIG. 1 is a plan view of a memory cell of a dynamic random access memory device according to the prior art. The memory cell includes one source channel type MOS transistor and one
It is a one-transistor type memory cell with two capacitances and is manufactured by a known method. In Fig. 1, 11 is a data line formed by a diffusion layer, 12 is a gate region, 13 is a gate electrode made of polycrystalline silicon, 14 is a capacitor part, and 15 is an electrode of the capacitor part made of polycrystalline silicon. be. Generally, the width A of the gate electrode is wider than the width B of the gate, and in consideration of manufacturing variations in photographic technology, the gate electrode protrudes above the field by about 3 mm on each side in the width direction of the gate. Therefore, when used in a large-capacity memory device, the method of configuring the memory cell is such that the width A of the gate electrode is used repeatedly at a period defined by the width A, so it is necessary to keep the width below a predetermined value or increase the manufacturing process. It cannot be densified. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a high-density semiconductor device by reducing the gate electrode width and reducing the size of a MOS transistor.

The structure of the present invention to achieve the above object is to form an insulating isolation region between each element on a semiconductor substrate, form a gate insulating film in the element region, and deposit, for example, polycrystalline silicon, which will become a gate electrode, on this. After that, the width of the gate electrode is formed by photo-etching, the channel stopper region is formed by introducing impurities, the length of the gate electrode is formed by a second photo-etching, and the source is formed by introducing impurities. , is fabricated by forming a drain region.

According to the method for manufacturing a semiconductor device according to the present invention, in a MOS transistor, the size of the gate electrode in the width direction is the same as the width of the gate region, so the size of each transistor can be made smaller than in the conventional case. It is possible to manufacture high-density, large-scale integrated circuit devices in high speed.

Next, preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a plan view of a one-transistor type memory cell completed according to an embodiment of the present invention.

Here, 21 is a data line of an impurity layer formed by diffusion, 22 is a gate region, 23 is a gate electrode made of polycrystalline silicon, and 26 is a channel stopper region.
Here, the width A of the gate electrode is made in a self-aligned manner to be the same size as the gate width of the MOS type transistor, so that the gate electrode width can be made smaller than in the case of a secondary structure. Furthermore, although the width of 8, which determines the repeat size of the memory cell, is drawn larger than A' in the figure, it may essentially be the same size as A', and if A' and B' are of the same size. In some cases, the channel stopper region 26 is formed only in a portion where the gate electrode and the gate do not overlap due to manufacturing variations. now,
In FIG. 2, the cross section taken along the line X-X' is taken as the cross section in the x direction, and the cross section taken along the line Y-Y is taken as the cross section in the Y direction.
3 to 7 sequentially show the manufacturing process of a memory cell according to the present invention, with FIG. 6 being a sectional view in the Y direction, and the remaining sectional views in the X direction.

FIG. 3 is a cross-sectional view in the x direction, in which a silicon dioxide film 32 with a thickness of 1㎜ is formed by selective oxidation using a known silicon nitride film on a P-type silicon substrate 31 with a resistivity of 150-skin. This figure shows the process of forming an insulating isolation region. FIG. 4 shows the process of forming the capacitor portion.

By thermal oxidation at 900°C, 500%
A silicon dioxide film was formed, a 0.5 m thick polycrystalline silicon film containing 1 and 3 phosphorus was deposited on it by vapor phase growth, and polycrystalline silicon and polycrystalline silicon were formed by photolithography. The silicon dioxide film is sequentially and selectively removed to form a gate insulating film 33 and a gate electrode 34 in the contact area.

FIG. 5 shows the process of forming the gate portion of a source-channel type transistor.

A 100-layer silicon dioxide film 35 is formed on the region that is to become a device by thermal oxidation at 900° C., and a 1.5-rm polycrystalline silicon film containing 1 Sugibushi-3 phosphorus is formed thereon by vapor phase growth. He wears 36.

FIG. 6 is a sectional view in the Y direction.

The polycrystalline silicon 36 only in the width direction of the MOS transistor is selectively removed using the photo-etching process using the photoresist 37, and with the silicon dioxide film 35 remaining, the polycrystalline silicon 36 is removed using the ion implantation method at 5+KeV. Poron 1 and 3-2 are implanted to form a channel stopper region 38 in a self-aligned manner in the width direction of the transistor. FIG. 7 is a cross-sectional view in the x direction.

MO by photolithography using photoresist 39 again.
The polycrystalline silicon 36 in the length direction of the S-type transistor is selectively removed to form a gate electrode 40 and a gate insulating film 41. Furthermore, using this photoresist 39, a source region 42 having a concentration of 1 P-3 is formed in a self-aligned manner in the length direction of the transistor by phosphorus ion implantation. Thereafter, a 0.5 mm silicon dioxide film is formed on the channel stopper region 38 and the source region 42 by a vapor phase growth method.
It is completed by performing metal wiring. Channel here
The formation of silicon dioxide pus on the stopper region and the source region 42 may be performed by simultaneous thermal oxidation or separate thermal oxidation steps. The same effect can be achieved even if it is used to manufacture a MOS type transistor having.

[Brief explanation of drawings]

FIG. 1 is a top view of a one-transistor memory cell according to the prior art. FIG. 2 is a plan view of a semiconductor device according to an embodiment of the present invention. 3 to 7 are cross-sectional views showing the manufacturing method according to an embodiment of the present invention in the order of steps, and FIGS. 3, 4, 5, and 7 are cross-sectional views of FIG. Figure 6 shows the part cut along X' and viewed in the direction of the arrow;
A portion viewed in the direction of the arrow along -Y is shown. still,
In the figure, 11 and 21 are data lines, 12 and 22 are gate regions, 13 and 23 are gate electrodes, 14 and 24 are capacitor regions, 15 and 25 are capacitor electrodes, 26 is a channel stopper region, and 31 is silicon. 3 is a substrate, 32 is a silicon dioxide film, 33 and 41 are gate insulating films, 34 is an electrode of a capacitive part, 35 is a silicon dioxide film, 36 is a polycrystalline silicon film, 3
7 and 39 are photo resists, 38 is a channel stopper region, 40 is a gate electrode, and 42 is a source. Ticket ``Doujin 2, 3, 4, Tsutsuzu, Chifu, Tafu, etc.''

Claims (1)

[Claims] 1. A step of forming a thick silicon oxide film for element isolation on a semiconductor substrate of one conductivity type, a step of providing a conductive layer extending in one direction and having a predetermined gate electrode width, and using the conductive layer as a mask the step of forming a thick silicon oxide film for element isolation. A step of introducing an impurity of one conductivity type between the silicon oxide film and a portion of the semiconductor substrate under the conductive layer, and patterning the length direction of the conductive layer so as to obtain a predetermined gate electrode. 1. A method of manufacturing a semiconductor substrate, comprising the step of introducing impurities of opposite conductivity type into the semiconductor substrate using longitudinal ends of the layer as a mask to form source and drain regions.