JPS6039893A - Method of connecting between upper and lower portions of multlayer circuit board - Google Patents
Method of connecting between upper and lower portions of multlayer circuit boardInfo
- Publication number
- JPS6039893A JPS6039893A JP14850883A JP14850883A JPS6039893A JP S6039893 A JPS6039893 A JP S6039893A JP 14850883 A JP14850883 A JP 14850883A JP 14850883 A JP14850883 A JP 14850883A JP S6039893 A JPS6039893 A JP S6039893A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- multlayer
- circuit board
- wiring board
- lower portions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔技術分野〕
本発明は多層配線板において上下の銀箔間を接続する方
法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for connecting upper and lower silver foils in a multilayer wiring board.
従来、間に絶縁層（１）を介在した複数層の銅箔（２）
をベース（３）に積層した多層配線板（〜に上下の銅箔
（２）間に亘る穴（４）をあけて上下の銅箔（２）間を
接続するに当っては第１図（ａ）に示すように半田（５
γを充填していたが、半田（５）′で接続すると第１図
（ｂ）に示すように半田（６１′が分離して接続の信頼
性が低くかつた。Conventionally, multiple layers of copper foil (2) with an insulating layer (1) interposed between them
When connecting the upper and lower copper foils (2) by making a hole (4) between the upper and lower copper foils (2) in the multilayer wiring board (~) laminated on the base (3), please refer to Figure 1 ( solder (5) as shown in a)
However, when connecting with solder (5)', the solder (61') separated as shown in FIG. 1(b), resulting in low connection reliability.
本発明は叙述の点に鑑みてなされたものであって、本発
明の目的とするところは接続信頼性が高く、しかも導通
抵抗の低い多層印刷板の上［間接続方法を提供するにあ
る。The present invention has been made in view of the above points, and an object of the present invention is to provide a method for connecting on a multilayer printing plate with high connection reliability and low conduction resistance.
〔発明の開示）
本発明は上下の銅箔（２）間を銅ペースト（６）にて接
続すると共に穴（４）に半田（５）を充填して従来例の
欠点を解決したものである。[Disclosure of the Invention] The present invention solves the drawbacks of the conventional example by connecting the upper and lower copper foils (2) with copper paste (6) and filling the holes (4) with solder (5). .
以下本発明を実施例により詳述する。多層配線板（Ｎは
片面多層配線板であって、開に絶縁接着剤のような絶縁
層ｆｌ）を介在した複数層の銅箔（２）を絶縁相のベー
ス（３）に積層して形成されている。本実施例の場合銅
箔（２）が２Ｍであるが、８層以上の複数層であっても
よい。しかして上下の銅箔（２）間を接続するに当って
、上下の銅箔（２）間に亘るように穴（４）をあけ、こ
の穴（４）を介して第２図（ａ）のようにト
銅ベース（６）にて」二下の銅箔（２）間を接続し、し
かるΔ
後第２図（ｂ）のように半田（５）を穴（４）に充填す
る０との際銅ペースト６）を用いると導通′＃肱が高い
が、半田（５）により導通抵抗を低くできる。また銅ペ
ースト（６）の代わりに銀ペーストを用いるととも考え
られるが、銀ペーストは導通抵抗が低い代わりに半田（
５）がイ１かない。また半田（５）は半田ペーストを用
いるか手半田で行なう。The present invention will be explained in detail below with reference to Examples. A multilayer wiring board (N is a single-sided multilayer wiring board, formed by laminating multiple layers of copper foil (2) with an insulating layer fl such as an insulating adhesive interposed) on an insulating base (3). has been done. In this example, the copper foil (2) is 2M, but it may be made of eight or more layers. In order to connect the upper and lower copper foils (2), a hole (4) is made spanning between the upper and lower copper foils (2), and the hole (4) shown in Figure 2 (a) is inserted through this hole (4). Connect the two lower copper foils (2) with the copper base (6) as shown in Figure 2(b), then fill the holes (4) with solder (5) as shown in Figure 2(b). If copper paste 6) is used in this case, the conduction resistance will be high, but the conduction resistance can be lowered by using solder (5). It is also possible to use silver paste instead of copper paste (6), but silver paste has low conduction resistance, but solder (
5) is not a1. Further, soldering (5) is performed using solder paste or by hand soldering.
さらに本発明の実施例のものと従来のものとを比較する
と下表のような性能の差がある。Furthermore, when comparing the embodiment of the present invention with the conventional one, there is a difference in performance as shown in the table below.
本発明は叙述の如く上下の銅箔間ｆ：銅ペーストにて接
続し、しかる後人に半田を充填しているので、導通の信
頼性が高い上、導通抵抗を低くくできて上下間を確実に
接続できるものである。In the present invention, as described above, the upper and lower copper foils are connected using copper paste and then filled with solder, so that the reliability of continuity is high and the conduction resistance can be lowered. It can be connected reliably.
第１図（ａ）（ｂ）は従来例の断面図、第２図（ａ）
（ｂ）は本発明の一実施例の断面図であって、（Ａ）は
多層配線板、＋１＋は絶縁層、（２）は銅箔、（３）は
ベース、（４）は穴、（５）は半田、（６）はｔｌｄｌ
＜−ストである。
代理人 弁理士 石 ｕｌ 長 七
（０）
（０）
図
（ｂ）
？ｑ）２ ）・コ
（ｂ）Figure 1 (a) and (b) are cross-sectional views of the conventional example, Figure 2 (a)
(b) is a sectional view of one embodiment of the present invention, in which (A) is a multilayer wiring board, +1+ is an insulating layer, (2) is a copper foil, (3) is a base, (4) is a hole, ( 5) is solder, (6) is tldl
<-It's a strike. Agent patent attorney stone ul long seven (0) (0) Figure (b)? q)2)・ko(b)
Claims (1)
積層した多層配線板に上下の銅箔間に亘たる穴をあけ、
上下の銅箔間を銅ペーストにて接続し、しかる抜穴に半
田を充填することを特徴とする多層配線板の上下間接続
方法。(1) Drill a hole spanning between the upper and lower copper foils in a multilayer wiring board made by laminating multiple layers of copper foil on a base with an insulating layer interposed between them,
A method for connecting upper and lower copper foils of a multilayer wiring board, characterized by connecting upper and lower copper foils with copper paste and filling corresponding punch holes with solder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14850883A JPS6039893A (en) | 1983-08-13 | 1983-08-13 | Method of connecting between upper and lower portions of multlayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14850883A JPS6039893A (en) | 1983-08-13 | 1983-08-13 | Method of connecting between upper and lower portions of multlayer circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6039893A true JPS6039893A (en) | 1985-03-01 |
Family
ID=15454327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14850883A Pending JPS6039893A (en) | 1983-08-13 | 1983-08-13 | Method of connecting between upper and lower portions of multlayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6039893A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0526598U (en) * | 1991-09-19 | 1993-04-06 | 日本発条株式会社 | Automatic rotating device for vehicle chair |
| JPH0554063U (en) * | 1991-09-25 | 1993-07-20 | 小糸工業株式会社 | Rotating lock mechanism for turning chairs for vehicles |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5140620A (en) * | 1974-10-02 | 1976-04-05 | Shinko Electric Co Ltd | Dendobarubu no kudosochi |
| JPS52112769A (en) * | 1976-03-19 | 1977-09-21 | Matsushita Electric Ind Co Ltd | Method of mounting leadless electric parts to circuit substrate |
-
1983
- 1983-08-13 JP JP14850883A patent/JPS6039893A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5140620A (en) * | 1974-10-02 | 1976-04-05 | Shinko Electric Co Ltd | Dendobarubu no kudosochi |
| JPS52112769A (en) * | 1976-03-19 | 1977-09-21 | Matsushita Electric Ind Co Ltd | Method of mounting leadless electric parts to circuit substrate |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0526598U (en) * | 1991-09-19 | 1993-04-06 | 日本発条株式会社 | Automatic rotating device for vehicle chair |
| JPH0554063U (en) * | 1991-09-25 | 1993-07-20 | 小糸工業株式会社 | Rotating lock mechanism for turning chairs for vehicles |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH05343855A (en) | Multilayer printed wiring board and manufacture thereof | |
| JPS6039893A (en) | Method of connecting between upper and lower portions of multlayer circuit board | |
| JP3203279B2 (en) | Flexible circuit board having a shield layer | |
| JP2002176263A (en) | Printed wiring board | |
| JPS60180186A (en) | Printed board | |
| JPS6018578U (en) | Wet multilayer ceramic substrate | |
| JPS60144990A (en) | Metal base circuit board | |
| JPS59191765U (en) | Wet multilayer ceramic substrate | |
| JPS6039896A (en) | Method of producing multilayer circuit board | |
| JP2514384Y2 (en) | Metal base wiring board | |
| JPS6362396A (en) | Construction of board with through-holes | |
| JPS59191764U (en) | Wet multilayer ceramic substrate | |
| JPS6066497A (en) | Multilayer printed circuit board | |
| JPS62155594A (en) | Multilayer printed circuit board | |
| JPS59168697A (en) | Method of producing metal base printed circuit board | |
| JPS61187396A (en) | Manufacture of printed wiring board | |
| JPS63196095A (en) | Manufacture of multilayer blind through-hole interconnection board | |
| JPS5948986A (en) | Mounting structure of electronic part on printed board | |
| JPS60242697A (en) | Method of producing multilayer circuit board | |
| JPS62145799A (en) | Multilayer wiring board | |
| JPS60240193A (en) | Multilayer circuit board | |
| JPS63185089A (en) | Printed wiring board | |
| JPS61263194A (en) | Surface-back conduction for double-side printed wiring board | |
| JPS5939960U (en) | printed wiring board | |
| JPS62145798A (en) | Multilayer substrate |