JPS603778B2 - semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a semiconductor integrated circuit which is intended to stably integrate elements with high breakdown voltage without deteriorating their characteristics.

FIG. 1 shows a part of a structural cross-sectional view of a conventional semiconductor integrated circuit using a diode as an example.

In FIG. 1, 1 is a semiconductor substrate, 2 is a semiconductor region having a relatively low impurity concentration to obtain a high breakdown voltage and is of a conductivity type opposite to that of the substrate 1, 3 is a region of a conductivity type opposite to that of the region 2, and 4 is a region. High impurity concentration region with the same conductivity type as 2 and provided to improve ohmic contact, 5 is a surface protective film, 61 and 6
Reference numerals 2 denote lead-out electrode wirings from regions 3 and 4, respectively.
Reference numeral 7 denotes an inversion layer in the region 2 where charges are accumulated with the protective film 5 interposed when an arbitrary potential is applied to the electrode wiring 61.

As an example, consider a state in which a negative potential V is applied to the electrode wiring 61 when regions 2 and 4 are n-type and region 3 is p-type.
Incidentally, the base body 1 may of course be an insulating substrate. Letting the dielectric constant of the insulating film 5 be t, and the thickness of the insulating film 5 to be t, a positive charge of Q=vx÷ is generated per unit area at the interface between the region 2 and the insulating film 5.

When region 2 is a substrate with relatively low impurity concentration, the surface of region 2 is inverted to p-type as the positive charge Q increases.
This inversion layer becomes a source of leakage, and the device exhibits various unstable characteristics. In order to solve this drawback, attempts have been made to adopt a dielectric constant of 4 mm or increase the thickness t of the insulating film 5, but the dielectric constant is It is difficult for an insulating film to have a thickness of less than 3.0 cm (G o = vacuum yield rate), and the maximum thickness t is around 5 microns, and wiring becomes difficult when it is larger than that.

The purpose of the present invention is to eliminate these drawbacks by interposing air between the surface protective film and the wiring to reduce the value of the capacitor, thereby preventing the formation of a surface inversion layer.
This relates to a semiconductor integrated circuit that stably integrates many high-voltage devices, and will be described in detail below. FIG. 2 shows a first embodiment of the present invention, in which 1 is a semiconductor substrate, 2 is a semiconductor region, 3 is a region of the opposite conductivity type to region 2, 4 is a high impurity concentration region, 5 is a surface protective film, 61 and 62 are the extraction electrode wiring, 8
is a gap between the surface protection film and the wiring according to the present invention.

An example of a manufacturing method for easily realizing the semiconductor integrated circuit of the present invention is shown in FIGS. 3A to 3C. Figure 3A, Figure 3B,
FIG. 3C is an example of a manufacturing method for easily realizing the semiconductor integrated circuit of the present invention.

First, in FIG. 3A, 11 is a semiconductor substrate, 21 is a semiconductor region, 31 is a region of the opposite electric type to the region 21, 41 is a high impurity concentration region, 51 is a surface protective film, and 52 is an etching liquid such as strong hydrofluoric acid. Therefore, it is desirable to use a film with a very strong masking effect, such as a silicon nitride film, but this is not always necessary depending on the case. Next, 53 in Figure 3B is
A film with a very fast etching rate (several thousand angstroms per second) for the etching solution, such as high concentration phosphorus glass, is suitable and is selectively left on the film 52. be. Next, in Figure 3C, 63, 64
is the extraction electrode wiring.

Aluminum, which is generally widely used, is suitable as a material. In FIG. 3C, the structure shown in FIG. 2 can be obtained by immersing the film 53 in an etching solution for several seconds. As explained above, according to the semiconductor integrated circuit of the present invention, the electrode wiring that crosses the PN junction surface, which may cause a small IJ current due to channel inversion, has a gap between the wiring and the surface protective film. Therefore, the amount of charge generated due to the wiring 61 at the interface between the semiconductor region 2 and the surface protection film 5, which has a low purity concentration as shown in FIG. If t is the thickness of the air gap 8 in FIG. 2, then Q・=C・V in FIG.
= Science xv In Fig. 2, Q2 = C2V x 1,000v, which is even lower than in the case of Fig. 1.

Conversely, according to the present invention, it is possible to stably integrate a device with a breakdown voltage three times that of the conventional device.

Furthermore, the semiconductor integrated circuit of the present invention is etched with hydrofluoric acid,
If the intermediate film is made of high-concentration phosphorus glass and the wiring material is made of aluminum, manufacturing is easy because only materials that are generally used in integrated circuit manufacturing are used. Good results can be obtained by etching using strong hydrofluoric acid and completing the etching in a few seconds. In the first embodiment, a diode is used as an example, but as shown in FIG. In some cases, the region 32 and the region 33 of the same conductivity type exist in a closed manner around the region 32 .

In FIG. 4, 54 is a surface protection film, and 65 and 66 are haze electrode wirings connected to the region 32 and the region 33, respectively.
81 is a void formed according to the present invention.

In this situation where the region 32 is surrounded by the region 33 and the wiring has to be drawn outside, the two regions 32 and 33 would not be able to interact with each other due to the generation of an inversion layer due to the wiring, unless the present invention is adopted. It becomes connected and loses its functionality completely. In this case, this problem can be solved by forming the void 81 according to the present invention. As described above, the present invention becomes more effective when applied to pnp transistors, thyristors, planar elements with guard rings, and the like. The present invention is suitable for integrating high-voltage devices because a gap is provided between the surface protection film and the wiring, making it difficult to form an inversion layer on the surface of a semiconductor substrate with a low impurity concentration.

[Brief explanation of the drawing]

FIG. 1 is a structural sectional view of a conventional semiconductor integrated circuit, FIG. 2 is a structural sectional view of a semiconductor integrated circuit according to the present invention, and FIG. 3A.
3B and 3C are manufacturing process diagrams showing a manufacturing example for easily realizing a semiconductor integrated circuit according to an embodiment of the present invention;
The figure is a structural sectional view of another embodiment of the present invention. 1, 1 1, 12... Semiconductor substrate or insulator substrate, 2, 21, 22... Semiconductor region with relatively low concentration impurity, 3, 31, 32... A semiconductor region having a conductivity type opposite to that of the semiconductor regions 2, 21, and 22 with relatively low concentration impurities, 33...A semiconductor region having the same conductivity type as the region 32,
Semiconductor region surrounding 4, 41... Semiconductor region with Takagi purity concentration of the same conductivity type as semiconductor regions 2, 21 with relatively low impurity concentration, 5, 51, 54... Surface Protective film, 52...Insulating film with strong masking effect against hydrofluoric acid, 63...Intermediate insulating film with high etching rate against hydrofluoric acid, 61, 62, 63, 64, 65, 66
...Exposed electrode lead-out wiring from the semiconductor regions 3, 4, 31, 41, 32, 33, 8, 81......Gap between the surface protection film and the military electrode lead-out wiring. Figure 1 Figure 2 Figure 3A Figure 3B Figure 3C Figure 4

Claims (1)

[Claims] 1. In a semiconductor device having a structure in which an electrode wiring layer on an insulating film formed closely on the surface of a semiconductor substrate extends across a plurality of PN junctions that partition the surface of the substrate into different conductivity types, A portion of the electrode wiring layer crossing over the insulating film formed on a surface of a conductivity type different from the conductivity type of the surfaces on both sides sandwiched by the plurality of PN junctions terminating at the surface has a gap between the electrode wiring layer and the insulating film. A semiconductor integrated circuit characterized in that it is formed so as to have the following characteristics.