JPS6037558B2 - Programmable read-only memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a new configuration of a programmable read only memory (hereinafter abbreviated as "PROM").

Conventionally, there are two types of PROM configurations: a junction breakdown type and a fuse type.

FIG. 1 is a circuit diagram showing an example of a conventional junction breakdown type PROM in a state before writing.

In the figure, W is a plurality of word lines provided parallel to the x direction and spaced apart from each other in the Y direction, and B is a plurality of bit lines provided parallel to the Y direction and spaced apart from each other in the x direction. , 101 connects the cathode of the diode D, which connects the anode of the diode D and the anode of the diode D2, to the bit line B at each intersection where a plurality of word lines W and bit lines B cross each other. This is a junction breakdown type PROM memory cell composed of anti-series connected diodes in which the cathode of D2 is connected to the word line W.

Note that normally, in the memory cell 101, an npn transistor composed of an n+ type emitter region, a p type base region, and an n type collector region is connected to a diode D, which is composed of the n+ type emitter region and the p type base region. Correspondingly, a diode consisting of a p-type base region and an n-type collector region is used in correspondence with the diode D2. FIG. 2 is a cross-sectional view showing the configuration of a memory cell of this conventional junction breakdown type PROM, and FIGS. 2A and 2B show the state before writing and the state after penetration, respectively.

In the figure, 1 is a p-type silicon (Si) substrate, 2 is an n-type epitaxially grown Si layer (hereinafter referred to as "n-type epitaxial layer J") formed on one main surface of the p-type Si substrate 1, and 3 is 4 is an n-type buried layer buried in the interface with the n-type epitaxial layer 2 of the p-type Si substrate 1 and constitutes the word line W shown in FIG. The formed p-type base region 5 is the p-type base region 4
A p-type isolation region 6 is formed on the surface of the p-type Si substrate 1 to surround the p-type base region 4 and reach from the surface of the n-type epitaxial layer 2 to the king side of the p-type Si substrate 1. The layer 7 is an insulating film formed over each surface of the n+ type emitter region 5, the p-type base region 4, the n-type epitaxial layer 2, and the p-type separation layer 6, and the layer 8 is an insulating film formed on the surface of the insulating film 7. This is an aluminum (AI) wiring that penetrates the insulating film 7 and is connected to the n+ type emitter region 5 and constitutes the bit line B shown in FIG.

The memory cell 101 of this junction destruction type PROM is composed of an npn transistor including an n+ type emitter region 5, a p type base region 4, and an n type epitaxial layer 2. Writing to the memory cell 101 of this cross-destruction type PROM is performed by injecting a large pulse current from the AI wiring 8 to the memory cell 101 and crossing the n+ type emitter region 5 from the AI wiring 8, as shown in FIG. 2B. p-type base region 4
This is done by forming a Si/mountain eutectic alloy layer 9 over the entire area, and breaking the emitter-base junction to short-circuit it.
By the way, in this junction destruction type PROM, memory cell 1
Since it is necessary to write by flowing a large pulse current into 01, it is not easy to miniaturize the memory cell 101, and there is a drawback that data cannot be rewritten.

FIG. 3 is a circuit diagram showing an example of a conventional fuse-type PROM in a state before writing.

In the figure, 102 is the joint breaking type PRO shown in Figure 1.
At each intersection where a plurality of bit lines B and word lines W similar to M cross each other, a diode D3 whose cathode is connected to the word line W is inserted between the anode of this diode D3 and the bit line B. This is a fuse-type PROM memory cell composed of a fuse F.

FIG. 4 is a sectional view showing the configuration of a memory cell of this conventional fuse-type PROM, and FIGS. 4A and 4B show the state before and after writing, respectively.

In the figure, the same reference numerals as those of the memory cell of the junction breakdown type PROM shown in FIG. 2 indicate the same parts, and the explanation thereof will be omitted.

10 is a p layer formed on the surface of the n-type epitaxial layer 2.
An anode electrode 1 made of N and connected to the p-type anode region 10' through the insulating film 7;
A fuse 2 is made of a loosely vapor-deposited metal such as a nickel (Ni)/chromium (Cr) alloy, is formed on the surface of the insulating film 7, and is inserted between the anode magnetic pole 11 and the AI wiring 8.

The memory cell 102 of this fuse-type PROM is composed of a diode 3 consisting of a p-type anode region 10 and an n-type epitaxial layer 2, and a fuse 12. Writing to the memory cell 102 of this fuse type PROM is as follows:
As shown in FIG. 4B, from the AI wiring 8 to the fuse 1 2
This is done by flowing a large pulse current into the diode D3 through the diode D3 to blow the fuse 12.

By the way, even in this fuse-type PROM, when writing, it is necessary to flow a large pulse current to the diode D3 to blow out the fuse 12, and in addition, the fuse 1
2 needs to be formed on the surface of the insulating film 7.
Similar to the memory cell 101 of the bond-break type PROM shown in the figure, it is not easy to miniaturize the memory cell 102, and furthermore, it has the disadvantage that data cannot be rewritten. This invention was made in view of the drawbacks of the junction destruction type PROM and the fuse type PROM mentioned above, and it is possible to reduce the size of the memory cell by making it possible to write with four current pulse voltages. possible,
Moreover, the new PRO allows data to be rewritten only once.
The purpose is to provide M.

FIG. 5 is a circuit diagram showing a state of a PROM according to an embodiment of the present invention before penetration.

In the figure, 103 is the fuse type PRO shown in Figure 3.
Similarly to M, at each intersection where a plurality of bit lines B and word lines W intersect with each other, a diode D3 similar to the memory cell 102 of a fuse-type PROM and an interlayer insulation between the anode of this diode D3 and the bit line B are provided. This is a memory cell of the PROM of this embodiment, which is composed of a pinhole PH formed in a film.

FIG. 6 is a cross-sectional view showing the structure of the memory cell of the PROM of this embodiment, and FIGS. 6A, B, and C show the state before writing, the state after writing, and the state after data rewriting, respectively.

In the figure, the same reference numerals as those of the memory cells of the junction destruction type PROM and the fuse type PROM shown in FIGS. 2 and 4 respectively indicate the same parts, and the explanation thereof will be omitted.

Reference numeral 13 denotes an interlayer insulating film formed on the surface of the insulating film 7 to cover the anode electrode 11 .

Note that the AI wiring 8 constituting the bit line B is connected to the glabella insulating film 1.
3, an n+ type buried layer 3 forming a word line W, a diode D3, an anode electrode 11 and an interlayer insulating film 1.
They are formed so as to intersect through 3. 14 is a/
The mountain wiring 8 is located at the part of the glabella insulating film 13 on the single electrode 11.
This is a pinhole that extends from the surface in contact with the anode electrode 11 and is formed so as not to reach the anode electrode 11.

The memory cell 103 of the PROM of this embodiment is composed of a diode D3 and a pinhole 14. Writing to the memory cell 103 of the PROM in this embodiment is performed by applying a pulse voltage between the mountain wiring 8 and the anode electrode 11 via the n+ type buried layer 3 and the diode D3, as shown in FIG. 6B. When the interlayer insulating film 13 directly under the pinhole 14 is dielectrically broken down, the A exposed wire 8 and the anode electrode 11 are caused by the micration of AI from the AI wiring 8 and the anode electrode 11 caused by this dielectric breakdown.
An AI connection film 15 is formed to connect the two, and the short circuit between the AI wiring 8 and the anode electrode 11 is performed by this AI connection film 15.

Therefore, in the PROM of this embodiment, writing can be performed with a small pulse voltage of a current that is only the voltage necessary for dielectric breakdown of the inter-dust insulating film 13 through the pinhole 14. The illustrated PROM
and memory cell 103 like a fuse-type PROM.
There is no need to apply a large pulse current to the memory cell 10.
3 of 4: You can take shape. Furthermore, when rewriting data, as shown in FIG. 6C, the anode electrode 1
A pulse current is passed between the AI on the glabellar insulation film 11.
This can be done only once by cutting the AI wiring 8 around the continuous film 15. This cutting of the AI wiring 8 can be easily performed with a small pulse current by concentrating the current from the AI wiring 8 to the AI connecting film 15 having a small cross-sectional area. As explained above, the PROM of this invention
Here, semiconductor layers of the second conductivity type in the first to nth rows are separated from each other by the first conductivity type region in the semiconductor substrate and constitute the word line W, and the semiconductor layers are formed on the semiconductor substrate with a glabella insulating film interposed therebetween. A pn junction is formed between the semiconductor layer and the semiconductor layer on the surface of the semiconductor layer at each intersection of the first to mth columns of aluminum wiring that intersect with each other and constitute a bit line. A first conductivity type semiconductor region having an aluminum electrode and constituting a memory cell is provided in the semiconductor region, and a pinhole is formed in a portion of the interlayer insulating film between the aluminum electrode and the aluminum wiring in the semiconductor region. Writing is performed by a short circuit caused by discharge between the aluminum wiring and the aluminum electrode through the pinhole, and if necessary, rewriting is performed by cutting the short circuit through the pinhole. A small pulse voltage with a current of only the voltage required to cause dielectric breakdown of the interlayer insulating film through the hole is sufficient, and during the rewriting, the cross-sectional area of the short circuit passing through the pinhole is extremely small, so this short circuit must be cut. This can be done with small pulsed currents.

Therefore, the secondary junction destruction type PROM and fuse type P
Unlike a ROM, there is no need to flow a large pulse current through the semiconductor region constituting the memory cell, and the memory cell can be made smaller. Furthermore, rewriting can be performed only once if necessary.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a conventional junction destruction type PROM before writing, and FIG. 2 is a sectional view showing the structure of a memory cell of the conventional junction destruction type PROM.
and B indicate the state before writing and the state after writing, respectively. FIG. 3 is a circuit diagram showing an example of a conventional fuse-type PROM before writing, and FIG. 4 is a cross-sectional view showing the structure of a memory cell of the conventional fuse-type PROM.
and B indicate the state before writing and the state after writing, respectively. FIG. 5 shows the PRO of one embodiment of this invention.
FIG. 6 is a circuit diagram showing the state before writing of M, and FIG.
Figures A, B, and C show the state before writing, the state after penetration, and the state after data rewriting, respectively. In the figure, 1 is a p-type Si substrate (first semiconductor layer of first conductivity type), 2 is an n-type epitaxial layer (second semiconductor layer of second conductivity type), and 2 is an n-type epitaxial layer (second semiconductor layer of second conductivity type).
6 is a p-type isolation scrap (the first semiconductor layer of the first conductivity type), 8 is the mountain wiring, and 10 is the p-type anode region (the first
11 is an anode electrode (AI electrode), 13 is an insulating film between scraps, 14 is a pinhole, 103 is a memory cell, W is a word line, and B is a bit line. In addition,
The same reference numerals in the figures indicate the same or corresponding parts.
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1 separated by a first semiconductor layer of the first conductivity type
second semiconductor layers of the second conductivity type in the first to nth rows that are arranged parallel to the (row) direction and spaced apart from each other in the Y (column) direction and constitute word lines; First to mth columns formed on the surface of the semiconductor layer at a distance from each other in the X direction, each having an aluminum electrode on the surface and forming a memory cell by joining with the second semiconductor layer. a group of semiconductor regions of the first conductivity type, and aluminum electrodes of the first to m-th columns forming bit lines, which are formed so as to face each of the aluminum electrodes of the semiconductor region groups of each column with an interlayer insulating film interposed therebetween. A wiring, and a pinhole formed in a portion of the interlayer insulating film between the aluminum wiring and the aluminum electrode opposing thereto, and a short circuit due to discharge through the pinhole between the aluminum wiring and the aluminum electrode. The programmable read-only memory is characterized in that the programmable read-only memory is configured to perform writing and, if necessary, to perform rewriting by cutting off the short circuit through the pinhole.