JPS6037119A - Plasma vapor phase reaction device - Google Patents

Plasma vapor phase reaction device

Info

Publication number
JPS6037119A
JPS6037119A JP58145266A JP14526683A JPS6037119A JP S6037119 A JPS6037119 A JP S6037119A JP 58145266 A JP58145266 A JP 58145266A JP 14526683 A JP14526683 A JP 14526683A JP S6037119 A JPS6037119 A JP S6037119A
Authority
JP
Japan
Prior art keywords
opened
electrode
region
electrodes
plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58145266A
Other languages
Japanese (ja)
Other versions
JPH0546094B2 (en
Inventor
Shunpei Yamazaki
舜平 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP58145266A priority Critical patent/JPS6037119A/en
Publication of JPS6037119A publication Critical patent/JPS6037119A/en
Priority to JP5061237A priority patent/JP2564748B2/en
Publication of JPH0546094B2 publication Critical patent/JPH0546094B2/ja
Granted legal-status Critical Current

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Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/505Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
    • C23C16/509Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges using internal electrodes

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To enable mass productivity, and to increase the growth rate of a film by forming an opened hole or an opened groove to an electrode, converging the electric line of force in the region of the opened hole or the opened groove and generating high luminance discharge. CONSTITUTION:A reactive gas is fed to a quartz hood 21 from 23, and passes through a reticulate electrode 2 and reaches to a positive column region 5. Substrates 1, 1 are disposed in the positive column region in parallel with the electric lines of force 5 while the backs are fast stuck mutually. The substrate takes a shape surrounded by a quartz cage. Paired electrodes 2, 3 are supplied with high-frequency energy from the outside, and electricity is discharged in a region 20 in which a uniform electric field is formed. First glow discharge in the uniform electric field region and second glow discharge having high luminance in opened holes or opened grooves 14 having planes or recessed shapes to other electrodes are generated simultaneously by forming the opened holes or the opened grooves 14 to the electrodes. Accordingly, plasma concentrates in the electrode central sections 20.

Description

【発明の詳細な説明】 この発明は、プラズマ気相反応方法(即ちプラズマ気相
被膜作製方法またはプラズマ・エツチング方法、以下単
にプラズマ・プロセス、即ちPP法という)に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a plasma vapor phase reaction method (ie, a plasma vapor phase coating method or a plasma etching method, hereinafter simply referred to as a plasma process, or PP method).

この発明はPP法であって、平行平板型の電極方式を用
い、さらに、被形成面を有する基板を陽光柱領域に配設
し、多量に被膜形成またはエツチングを行う方法に関す
る。
The present invention relates to a PP method, in which a parallel plate type electrode system is used, a substrate having a surface to be formed is disposed in a positive column region, and a large amount of film is formed or etched.

従来、平行平板型のpp法においては、その被形成面を
陰極(カソード)または陽極(アノード)上またはこれ
らの電極のごく近傍に発生する陰極暗部または陽極暗部
を用いる方式が知られている。
Conventionally, in the parallel plate type pp method, a method is known in which the surface to be formed uses a cathode dark region or an anode dark region generated on or in the close vicinity of a cathode or anode.

かかる従来より公知の方式においては、電極面積の大き
さよりも被形成面の面積を大きく有せしめることができ
ない。このため、大面積の基板上に半導体、絶縁体また
導体被膜を作製することができるという特長を有しなが
らも、電極面積の5〜30倍もの被形成面を有せしめる
ことができない。
In such conventionally known methods, the area of the surface to be formed cannot be made larger than the area of the electrode. Therefore, although it has the advantage of being able to produce a semiconductor, insulator, or conductor film on a large-area substrate, it is not possible to have a surface on which it is formed that is 5 to 30 times the area of the electrode.

即ち、多量生産ができないという欠点を有していた。That is, it has the disadvantage that it cannot be mass produced.

このため、アモルファス・シリコンを含む非単結晶半導
体をPCVD法により作製せんとする時、その基板1−
あたりの製造価格が1円以上と高価となり、太陽電池等
の単価が安価な製品作製に応用することができないとい
う大きな欠点を有する。
For this reason, when trying to fabricate a non-single crystal semiconductor containing amorphous silicon by the PCVD method, the substrate 1-
It has a major drawback in that it is expensive, with a manufacturing price of 1 yen or more per unit, and cannot be applied to manufacturing inexpensive products such as solar cells.

加えて、被膜形成速度も1〜2人/秒と十分とはいえず
、これらの点より、多量生産性を有しかつ被膜成長速度
が3〜lO人/秒と大きいPCVD法がめられていた。
In addition, the film formation rate was not sufficient at 1 to 2 people/second, and from these points, the PCVD method, which has high productivity and a high film growth rate of 3 to 10 people/second, was desired. .

本発明はかかる目的を成就するためになされたものであ
る。
The present invention has been made to achieve this object.

即ち、本発明方法はプラズマ・グロー放電の陽光柱を用
いたものである。本発明は陽光柱領域に被形成面を有す
る基板を平行に互いに離間して配設したものである。か
かる陽光柱を用いたpcvo法に関しては、本発明式の
出願になる特許願57−163729、57−1637
30 (プラズマ気相反応装置〉(昭和57年9月20
日出願)に記されている。
That is, the method of the present invention uses a positive column of plasma glow discharge. In the present invention, substrates having formation surfaces in the positive column region are arranged in parallel and spaced apart from each other. Regarding the PCVO method using such a positive column, patent applications 57-163729 and 57-1637, which are filed in accordance with the present invention,
30 (Plasma gas phase reactor) (September 20, 1982)
(Applications filed in Japan).

本発明はかかる陽光柱にて反応をせしめ、多量生産を行
うものである。しかし陽光柱は一般に大きく空間に広が
るため、被形成面近傍でのプラズマ密度が減少し、結果
として暗部を用いる方式とおなし程度の被膜成長速度し
か得られないという他の欠点を有する。
The present invention allows the reaction to take place in such a positive light column, thereby achieving mass production. However, since the positive column generally spreads out over a large space, the plasma density near the surface to be formed decreases, and as a result, this method has another drawback in that a film growth rate comparable to that of a method using a dark region can be obtained.

かかる欠点を除去して、陽光柱を収束(しまらせる)せ
しめ、即ち、放電プラズマのひろがりを押さえ、さらに
中央部でのプラズマ密度を増加させ、活性反応性気体を
増加し、ひいては被膜成長速度を2〜3倍にまで大きく
することを特長としている。
By removing such defects, the positive column can be converged, that is, the spread of the discharge plasma can be suppressed, and the plasma density in the center can be increased, the active reactive gas can be increased, and the film growth rate can be improved. It is characterized by increasing the size by 2 to 3 times.

第1図は従来方法での平行平板型の電極(2)。Figure 1 shows a parallel plate type electrode (2) in the conventional method.

(3)およびその電気力線(5)、またこの電気力線に
直行する等電位面(15)を示している。そしてこれら
の電極は減圧下の反応容器(4)内に配設されており、
この電極の一方から(7)より供給された反応性気体(
6)が放出され、他方の基板(1)の被形成面上に被膜
形成される。
(3), its lines of electric force (5), and an equipotential surface (15) that is perpendicular to the lines of electric force. These electrodes are placed in a reaction vessel (4) under reduced pressure,
A reactive gas (7) is supplied from one side of this electrode.
6) is released and a film is formed on the surface of the other substrate (1).

第2図(A)において、電極(2)、(3)間には高周
波電源(10)より13.56Ml1zが加えられる。
In FIG. 2(A), 13.56 Ml1z is applied between the electrodes (2) and (3) from the high frequency power source (10).

不要反応生成物は排気系(8)にてバルブ(11)、圧
力調整バルブ(12)、真空ポンプ(13)より外部に
排気される。
Unnecessary reaction products are exhausted to the outside through a valve (11), a pressure regulating valve (12), and a vacuum pump (13) in an exhaust system (8).

かかる従来の方法においては、電気力線(5)は被形成
面に垂直に加わるため、被形成面をスバンタ(損傷)し
てしまうという他の欠点を有する。
This conventional method has another drawback in that the electric lines of force (5) are applied perpendicularly to the surface to be formed, thereby damaging the surface to be formed.

第1図(B)は第1図(A)の電極の一方(2)に対し
針状電極(9)を互いに離間して配設したものである。
In FIG. 1(B), needle-like electrodes (9) are arranged at a distance from one of the electrodes (2) in FIG. 1(A).

ここでは電極(2X50cn+ X 50cm)、電極
(2>、(3)の間隔4cm、針状電極長さ1cm、間
隔5cmとした。かかる針状電極を第1図(A)の装置
に配設した時も、電気力線は針状電極より分散し、ひろ
がる方向に供給され、基板(1)に垂直に加えられる。
Here, the electrodes (2 x 50 cn + x 50 cm), the spacing between the electrodes (2>, (3)) was 4 cm, the length of the needle-shaped electrodes was 1 cm, and the spacing was 5 cm. Such needle-shaped electrodes were arranged in the apparatus shown in Fig. 1 (A). At the same time, the electric lines of force are distributed from the needle-shaped electrode and are supplied in a spreading direction, and are applied perpendicularly to the substrate (1).

等電位面(15)は電気力線と直行して設けられるにす
ぎない。このため、針状電極は第1図(A)に装置に配
設した場合でも放電開始を容易にする等の特長をそれな
りに有しながらも、被膜の膜質、被膜成長速度を向上さ
せるものではなかった。
The equipotential surfaces (15) are only provided perpendicular to the lines of electric force. For this reason, even when the needle electrode is installed in the device shown in Figure 1 (A), although it has certain features such as facilitating discharge initiation, it does not improve the film quality or film growth rate of the film. There wasn't.

第2図は本発明のPP法即ちPCVD法またはプラズマ
・エツチング法における電極およびその概要を示したも
のである。この反応炉の他部は前記した本発明式の特許
願に準じる。
FIG. 2 shows an electrode and its outline in the PP method of the present invention, that is, the PCVD method or the plasma etching method. The other parts of this reactor conform to the above-mentioned patent application of the present invention type.

図面において、この一対の網状電極(2>、< 3 >
および被形成面を有する基板(1)、(1’)を有する
In the drawing, this pair of mesh electrodes (2>, <3>
and a substrate (1), (1') having a surface to be formed.

反応性気体の供給は(23)より石英フード(21)に
至り、網状電極(2)を通って陽光柱領域(5)に至る
。陽光柱領域には裏面を互いに密接して電気力線(5)
に平行に基板(1)、(1)を配役せしめである。また
この基板を石英カゴで取り囲む形状を有せしめである。
The supply of reactive gas (23) leads to the quartz hood (21) and through the mesh electrode (2) to the positive column region (5). In the positive column area, electric lines of force (5) are placed on the back side in close contact with each other.
The substrates (1), (1) are placed parallel to the . Furthermore, this substrate is surrounded by a quartz cage.

反応生成物の排気は下側フード(22)を経て排気(2
4)させる。
The reaction product is exhausted through the lower hood (22) and then to the exhaust (2).
4) Let.

一対を為す電極(2)、(3)には外部より高周波エネ
ルギが供給され、平等電界が形成される領域(10)に
放電がされる。
High frequency energy is supplied from the outside to the pair of electrodes (2) and (3), and a discharge is generated in a region (10) where an equal electric field is formed.

この図面では電極面積は25cmφ(電極間隔15cm
)才たは70cm X 70cn+ (電極間隔35c
m)の形状を有せしめ、さらにこの電極に開孔またば開
溝(14)を形成することにより、本発明の平等電界領
域での第1のグロー放電と開孔または開溝(14)に高
輝度の第2のグロー放電とを同時に発生せしめた。
In this drawing, the electrode area is 25cmφ (electrode spacing 15cm
) 70cm x 70cn+ (electrode spacing 35c)
m), and by forming an opening or groove (14) in this electrode, the first glow discharge in the uniform electric field region of the present invention and the opening or groove (14) are formed. A high-intensity second glow discharge was generated at the same time.

この図面より明らかなごとく、下側電極(13)は例え
ば単に開孔または開溝(0,5〜3cm例えば約1cm
φまたは約ICll1中)で作ったにすぎない。また他
の例では上側電極のごとく、この開孔または開溝を陽光
柱とは逆方向に曲面(16)を設け、凹状態をしている
As is clear from this drawing, the lower electrode (13) is, for example, simply a hole or groove (0.5-3 cm, for example about 1 cm).
φ or about ICll1). In another example, as in the case of the upper electrode, this opening or groove is provided with a curved surface (16) in the opposite direction to the positive column, and is in a concave state.

第1図(B)に示すごとく、針状即ち放電面に凸状態で
はな(、逆に本発明装置においては、電極を平面または
凹状にすることにより、電気力線(5)が領域(17)
、(18)において収束し、高密度電束領域が発生する
こ゛とがわかる。かくのごと(にすることにより、従来
より知られた平等電界により発生する第1のプラズマ放
電(27>、(28)に加えて高密度電束の発生により
、高輝度の第2のプラズマ領域(17>、(1B )を
同時に発生させることができた。
As shown in FIG. 1(B), the lines of electric force (5) are not acicular, that is, convex on the discharge surface (on the contrary, in the device of the present invention, by making the electrodes flat or concave, the lines of electric force (5) are in the region (17 )
, (18), and a high-density electric flux region is generated. By doing this, in addition to the first plasma discharge (27>, (28)) generated by the conventionally known uniform electric field, a high-intensity second plasma region is generated due to the generation of high-density electric flux. (17>, (1B)) could be generated simultaneously.

その結果、従来、陽光柱(25)では横方向への広がり
が大きく、プラズマが分散していたのが、本発明のPP
装置において電極中央部(20)内に集まる(35)傾
向を有せしめる午とができた。
As a result, while conventionally the positive column (25) had a large horizontal spread and the plasma was dispersed, the present invention's PP
A layer was created which had a tendency to collect (35) in the electrode center (20) in the device.

さらにこの高輝度プラズマの第2の放電を行わしめるこ
とにより、被膜成長速度を2〜3倍にすることができた
Furthermore, by performing a second discharge of this high-intensity plasma, the film growth rate could be doubled or tripled.

例えば100%シランを用い、0.1torr 、 3
0W(13,56MHz)、電極面を25cmφとし、
電極間隔15cm口 とした時、基板を10cm+ + 6枚を配設(延べ面
積600aa)において、開孔または開溝(14)を有
しない場合、被膜成長速度は1〜2人/秒であったが、
この開孔または開溝(14)を各電極に数ケ所設けるの
みで4〜6人/秒と2〜3倍に増加させることが可能に
なった。
For example, using 100% silane, 0.1 torr, 3
0W (13,56MHz), the electrode surface is 25cmφ,
When the electrode spacing was 15 cm, the film growth rate was 1 to 2 people/sec when there were no openings or grooves (14) when 6 substrates were arranged at 10 cm + + (total area 600 aa). but,
By simply providing several holes or grooves (14) on each electrode, it has become possible to increase the number of people per second by two to three times to 4 to 6 people per second.

このことは第1図の従来の方式に比べて、5〜20倍も
基板の配設量を大きくすることができるに加えて、被膜
形成速度を2〜3倍も高めることができ、2重に優れた
もめであることがわかる。
Compared to the conventional method shown in Figure 1, this not only allows the amount of substrate to be disposed to be 5 to 20 times larger, but also increases the film formation speed by 2 to 3 times, resulting in double It can be seen that it is an excellent struggle.

さらに加えて、陽光柱が収束することの結果、この陽光
柱が反応炉の内壁をスパツクし、この内壁に吸着してい
る水、付着物の不純物を活性化して被膜内に取り込み、
その膜質を劣化させる可能性をさらに少なくすることが
できるという点を考慮すると、三重にすぐれたものであ
ることが判明した。
In addition, as a result of the convergence of the positive light column, this positive light column splashes the inner wall of the reactor, activating water adsorbed on the inner wall and impurities attached to it, and incorporating it into the coating.
Considering the fact that the possibility of deteriorating the film quality can be further reduced, it has been found to be triple superior.

なお、以上の説明において、半導体被膜の作製について
のみ記した。しかし陽光柱に用いたプラズマ・エツチン
グに対しても、本発明方法を用いることは有効である。
In addition, in the above description, only the preparation of the semiconductor film was described. However, it is also effective to use the method of the present invention for plasma etching used for positive columns.

即ち、エツチングがされる基板に対し、CFjBr 、
 CHFJ等のエツチング気Wを導入し、基板上の被加
工面に対し、この基板表面に平行方向に異方性エツチン
グを行わんとすると、本発明方法は特に有効である。即
ち、プラズマ・エツチングは基板に垂直方向に深(異方
性エンチングすることのみがめられている。しかし基板
の凸部を平坦にするために選択的にエツチングをぜんと
する時、電界(電束ンが基板に平行方向であり、かつC
−F結合という高い結合エネルギを有する結合手にとっ
て、分解してラジカルに形成させるに十分なエネルギを
有せしめる、いわゆる一段のグロー放電に加えて高輝度
プラズマ放電をさせることにより、Fのラジカルを多量
に得ることができ、基板状の凸部のみに選択エツチング
を行うことができ、特に有効に実施させることができた
That is, for the substrate to be etched, CFjBr,
The method of the present invention is particularly effective when an etching gas W such as CHFJ is introduced to perform anisotropic etching on a surface to be processed on a substrate in a direction parallel to the surface of the substrate. That is, plasma etching is only supposed to cause deep (anisotropic etching) in the vertical direction of the substrate. is parallel to the substrate, and C
A high-intensity plasma discharge is generated in addition to a so-called one-stage glow discharge, which provides enough energy for the -F bond, which has a high bonding energy, to decompose and form radicals, thereby generating a large amount of F radicals. It was possible to perform selective etching only on the convex portions of the substrate, and the etching could be carried out particularly effectively.

以下にさらに実施例を加えて本発明を補完する。The present invention is supplemented by further adding Examples below.

実施例1 第2図を用いたPCVD法において、珪素を形成させた
場合を示す。番号は第2図に対応している。
Example 1 A case is shown in which silicon is formed by the PCVD method using FIG. 2. Numbers correspond to FIG.

図面において、下側の網状電極(3)に高輝度プラズマ
放電領域゛を3箇所、上側に4箇所を設けたものである
。基板(1)は石英ホルダ内に配設され、この冶具が3
〜5回/分で回転している。
In the drawing, three high-intensity plasma discharge areas are provided on the lower mesh electrode (3) and four areas on the upper side. The substrate (1) is placed in a quartz holder, and this jig is
It rotates at ~5 times/minute.

反応性気体としてシランにより非単結晶珪素を作製した
。即ち、基板温度210℃、圧力01口orr。
Non-single crystal silicon was prepared using silane as a reactive gas. That is, the substrate temperature was 210°C and the pressure was 01 orr.

シラン30cc/分、放電出力30W (13,56P
IIIz)とし、5000 Aの厚さを有せしめるのに
20分、被膜成長速度は4.1人/秒を有している。
Silane 30cc/min, discharge output 30W (13,56P
IIIz), it takes 20 minutes to reach a thickness of 5000 A, and the film growth rate is 4.1 people/sec.

基板の配設されている石英ホルダの外側空間には何等放
電が見られず、反応容器のステンレス壁面をスパツクし
、水等の不純物を混入させる可能性が少ないことがわか
る。
No discharge was observed in the space outside the quartz holder where the substrate was placed, indicating that there was little possibility of spattering the stainless steel wall of the reaction vessel and introducing impurities such as water.

基板として、10cm X 10c+aA’ 6枚配設
され、反応性気体の収率(被膜となる成分/供給される
気体等)も第1図(A)に示すごとき形状に加えて8倍
近くになった。さらに第2図において開孔または開溝(
14)を設けない場合に比べて2倍に高めることができ
た。
Six 10cm x 10c+aA' substrates are arranged, and the yield of reactive gas (components forming the film/supplied gas, etc.) is nearly 8 times that of the shape shown in Figure 1 (A). Ta. Further, in Fig. 2, apertures or grooves (
14) was able to be doubled compared to the case where it was not provided.

実施例2 この第3図はメタン(CI!4)とシラン(SiH4)
とを1 : 1(7)割合で混入し、5ixC+−t(
0<x< 1)の被膜を作製したものである。
Example 2 This figure 3 shows methane (CI!4) and silane (SiH4)
and 1:1(7) ratio, 5ixC+-t(
A film with 0<x<1) was prepared.

図面に高輝度プラズマ放電が開溝部に観察された。そし
てかかる局gB放電がない場合に比べて、炭化珪素とな
る5i−C結合が多量にあり、化学的エツチングが起こ
っても、固い緻密な膜となっていた。その他は実施例1
と同様である。
In the drawing, a high-intensity plasma discharge was observed in the open groove. Compared to the case without such local gB discharge, there were a large amount of 5i-C bonds that became silicon carbide, and even if chemical etching occurred, the film remained hard and dense. Others are Example 1
It is similar to

実施例3 この実施例は第2図をプラズマ・エツチングとして用い
た場合である。
Embodiment 3 This embodiment is a case where FIG. 2 is used as plasma etching.

第3図において、凸部の頂点の窒化珪素膜を除去する場
合を示す。第3図(A)に示ずごと(、シリコン単結晶
基板(1)の表面が凸部(3)rlll〜2μと凹部(
1〜2μ)とを有している。その深さは1.5μとした
。さらにその上面に窒化珪素(31)を1000人の厚
さに形成し、次にレジスト(32)をコードンた。
FIG. 3 shows the case where the silicon nitride film at the apex of the convex portion is removed. As shown in Figure 3 (A), the surface of the silicon single crystal substrate (1) has convex portions (3) rllll~2μ and concave portions (
1 to 2μ). The depth was 1.5μ. Furthermore, silicon nitride (31) was formed to a thickness of 1000 nm on the upper surface, and then a resist (32) was coated.

次に第2図の装置により、図面に垂直方向(基板の表面
に平行)のプラズマをCF5 Brに5%の酸素を添加
した。このプラズマの周波数は30KHzと低くした。
Next, using the apparatus shown in FIG. 2, 5% oxygen was added to the CF5 Br using plasma in a direction perpendicular to the drawing (parallel to the surface of the substrate). The frequency of this plasma was set as low as 30 KHz.

すると第3図(B、)に示すごとく・凸部(33)のレ
ジスト(32)のみを除去することができた。さらに窒
化珪素を除去し、レジストを公知の方法により除去して
第3図(C)を得た。
Then, as shown in FIG. 3(B), only the resist (32) on the protrusion (33) could be removed. Furthermore, the silicon nitride was removed and the resist was removed by a known method to obtain FIG. 3(C).

この後、この凸部に選択的に不純物を混入する等の工程
を有せしめることにより、種々の半導体ディバイスを作
ることができた。
Thereafter, by performing a process such as selectively mixing impurities into the convex portions, various semiconductor devices could be manufactured.

実施例4 この実施例はシリコン単結晶が凹凸を有し、上面を平坦
にし、凹部に酸化珪素を充填した場合である。即ち、第
3図(A)に示したごとく、凹凸の基板上に窒化珪素(
33)および酸化珪素(32)を積層して形成した。
Example 4 In this example, a silicon single crystal has irregularities, the upper surface is made flat, and the recesses are filled with silicon oxide. That is, as shown in FIG. 3(A), silicon nitride (
33) and silicon oxide (32) were laminated.

この後、この第2図に示す基板表面に平行に電界を加え
るプラズマ・エツチング装置により、凸部を除去し、第
3図(B)に示すごとく、半導体にとっての凸部(33
)および凹部(34)の上面に酸化珪素(23)を残有
して、これらの上面を平坦にした。
Thereafter, the protrusions are removed using a plasma etching device that applies an electric field parallel to the substrate surface as shown in FIG. 2, and the protrusions (33
) and the recess (34), with the silicon oxide (23) remaining on the upper surfaces of the recesses (34) to make these upper surfaces flat.

実施例5 この実施例はVLSIにおける電極部の凹部を除去した
場合である。即ち、導体により電極部の凹部を充填して
、実質的に電極リードパターンを形成した場合を示す。
Embodiment 5 This embodiment is a case where the concave portion of the electrode portion in a VLSI is removed. That is, a case is shown in which the concave portion of the electrode portion is filled with a conductor to substantially form an electrode lead pattern.

第4図において、半導体表面(1)には埋置したフィー
ルド絶縁物(36)、ソース、ドレイン領域(37)、
(38とゲイト(39)、層間絶縁物(41)、1〜2
μφの開孔(42><深さネ0.5〜2μ)を有する。
In FIG. 4, the semiconductor surface (1) includes a buried field insulator (36), source and drain regions (37),
(38 and gate (39), interlayer insulator (41), 1-2
It has an opening (42><depth 0.5 to 2μ) of μφ.

この電極部にリード(43)を形成せんとしても、開溝
部(42)での凹部のため、2μまたはそれ以下の細い
パターンを電子ビーム露光技術を用いても切ることがで
きない。このため、この実施例にてはこれの全面に珪素
が添加されたアルミニューム(43)を0.5〜2μの
厚さに形成した。するとこのアルミニュームには凹部(
40)を有する。さらにこの基体を第2図に示す装置に
て異方性プラズマ・エツチングをCCI、の反応性気体
を用い凸部(33)を除去した。かくして凹部(34入
凸部の上面を概略平坦に第4図(B)のごとくにした。
Even if a lead (43) is not formed in this electrode portion, it is not possible to cut a thin pattern of 2μ or less even by using electron beam exposure technology because of the recess in the opening groove (42). For this reason, in this embodiment, silicon-doped aluminum (43) was formed on the entire surface to a thickness of 0.5 to 2 .mu.m. Then, this aluminum has a recess (
40). Further, this substrate was subjected to anisotropic plasma etching using the apparatus shown in FIG. 2 using reactive gas of CCI to remove the protrusions (33). In this way, the upper surface of the concave portion (34-convex convex portion) was made approximately flat as shown in FIG. 4(B).

するとアルミニュームは開孔部(42)に選択的に残り
、かつその上面を(33)、(34)において概略平面
とすることが可能となった。このため、この上面にさら
に第2のアルミニューム(44)を銅を添加して0.2
〜0.5μの厚さに形成させた。
This made it possible for the aluminum to selectively remain in the openings (42) and to make the upper surfaces of the holes (33) and (34) substantially flat. For this reason, a second aluminum (44) was further added to the top surface and copper was added to 0.2
It was formed to a thickness of ~0.5μ.

この後、公知の垂直方向の異方性エツチングを行うプラ
ズマ・エツチング装置により、1〜2μの細巾のパター
ンのリードを得ることができた。
Thereafter, a lead pattern with a width of 1 to 2 .mu.m could be obtained using a known plasma etching device that performs anisotropic etching in the vertical direction.

第4図、第3図は半導体素子を基板に垂直方向に重合わ
せる三次元ディバイスの作製にきわめて需要なものであ
る。
FIGS. 4 and 3 are extremely necessary for the fabrication of three-dimensional devices in which semiconductor elements are vertically superimposed on a substrate.

以上のように、本発明は第2図に示されるごと<、pp
装置において、電極に開孔または開溝を設け、この領域
で電気力線を収束せしめ、高輝度放電を発生せしめたも
のである。かかる方式は第1図のごと(、平行平板電極
上に基板を配設した場合、この基板の一部に高い電束反
応領域を有せしめてもよい。しかし、高輝度放電による
スバッタ効果を考慮する時、この放電に被形成面を配設
して、そのスパック(損傷)を少なくすることは膜質の
向上に有効であり、結果として本発明方法は陽光柱で基
板を電気力線に平行に配設するPP法に特に有効である
ことがわかった。
As described above, the present invention is as shown in FIG.
In this device, an aperture or groove is provided in the electrode, and lines of electric force are converged in this region to generate a high-intensity discharge. Such a method is shown in Fig. 1 (If a substrate is disposed on parallel plate electrodes, a part of this substrate may have a high electric flux reaction area. However, it is necessary to take into account the spatter effect due to high intensity discharge. It is effective to improve the film quality by arranging the surface to be formed on this discharge and reducing its spackle (damage).As a result, the method of the present invention allows the substrate to be parallel to the lines of electric force in the positive column. It has been found that this method is particularly effective for the PP method.

また本発明の実施例は非単結晶St、また5ixC+1
である。しかしシランとゲルマンを用いて5ixGe+
叉(0くx<1>、シランと塩化スズとを用いてSμs
n(<(0くx≦1)であっても有効である。AIをA
 I CI。
Further, the embodiments of the present invention include non-single crystal St, and 5ixC+1
It is. However, using silane and germane, 5ixGe+
(0x<1>, Sμs using silane and tin chloride
It is valid even if n(<(0x≦1).
ICI.

により、またSi八をS iH4とNIらとにより、5
iO1Iを5fltlとNLOとにより形成する場合等
の絶縁膜をPCVD法で作製する、またはプラズマ・エ
ツチング法により選択的にSiO*ISt+5t)N4
+フオトレジストその他化合物半導体を除去する場合に
も本発明は有効である。
5 by SiH4 and NI et al.
When forming iO1I with 5fltl and NLO, an insulating film is produced by PCVD method, or selectively SiO*ISt+5t)N4 by plasma etching method.
The present invention is also effective in removing photoresists and other compound semiconductors.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のプラズマ気相反応装置を示す。 第2図は本発明方法のプラズマ気相反応装置の電極基板
近傍の概要である。 第3図、第4図は本発明装置を用いて半導体装置を作製
した他の実施例を示す。 特許出願人 CA) CD) (CJ (A) (11)
FIG. 1 shows a conventional plasma vapor phase reactor. FIG. 2 is an outline of the vicinity of the electrode substrate of the plasma vapor phase reactor according to the method of the present invention. FIGS. 3 and 4 show other embodiments in which a semiconductor device was manufactured using the apparatus of the present invention. Patent applicant CA) CD) (CJ (A) (11)

Claims (1)

【特許請求の範囲】 1、平行平板型プラズマ・グロー放電を用いる気相反応
装置において、一対の電極の少なくとも一方の電極から
他方の電極に向かって電気力線が集中する電極領域を前
記一対の平板の電極の一部に開孔または開溝を設けるこ
とにより構成せしめたことを特徴とするプラズマ気相反
応装置。 2、特許請求の範囲第1項において、開孔または開溝ば
その端部が他方の電極に対して平面または凹型を有した
ことを特徴とするプラズマ気相反応装置。
[Claims] 1. In a gas phase reaction device using a parallel plate type plasma glow discharge, an electrode region where lines of electric force are concentrated from at least one of a pair of electrodes toward the other electrode is A plasma vapor phase reaction device characterized in that it is constructed by providing a hole or a groove in a part of a flat electrode. 2. A plasma vapor phase reactor according to claim 1, characterized in that the end of the opening or groove has a flat or concave shape relative to the other electrode.
JP58145266A 1983-08-08 1983-08-08 Plasma vapor phase reaction device Granted JPS6037119A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP58145266A JPS6037119A (en) 1983-08-08 1983-08-08 Plasma vapor phase reaction device
JP5061237A JP2564748B2 (en) 1983-08-08 1993-02-26 Plasma vapor phase reaction apparatus and plasma vapor phase reaction method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP58145266A JPS6037119A (en) 1983-08-08 1983-08-08 Plasma vapor phase reaction device
JP5061237A JP2564748B2 (en) 1983-08-08 1993-02-26 Plasma vapor phase reaction apparatus and plasma vapor phase reaction method

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP5061237A Division JP2564748B2 (en) 1983-08-08 1993-02-26 Plasma vapor phase reaction apparatus and plasma vapor phase reaction method

Publications (2)

Publication Number Publication Date
JPS6037119A true JPS6037119A (en) 1985-02-26
JPH0546094B2 JPH0546094B2 (en) 1993-07-13

Family

ID=26402288

Family Applications (2)

Application Number Title Priority Date Filing Date
JP58145266A Granted JPS6037119A (en) 1983-08-08 1983-08-08 Plasma vapor phase reaction device
JP5061237A Expired - Lifetime JP2564748B2 (en) 1983-08-08 1993-02-26 Plasma vapor phase reaction apparatus and plasma vapor phase reaction method

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Application Number Title Priority Date Filing Date
JP5061237A Expired - Lifetime JP2564748B2 (en) 1983-08-08 1993-02-26 Plasma vapor phase reaction apparatus and plasma vapor phase reaction method

Country Status (1)

Country Link
JP (2) JPS6037119A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05144595A (en) * 1991-11-22 1993-06-11 Semiconductor Energy Lab Co Ltd Plasma processing device
JPH0620976A (en) * 1983-08-08 1994-01-28 Semiconductor Energy Lab Co Ltd Plasma vapor phase reactor and plasma vapor phase reaction method
JPH06140347A (en) * 1993-05-13 1994-05-20 Semiconductor Energy Lab Co Ltd Plasma vapor growth reaction method

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10392135B2 (en) 2015-03-30 2019-08-27 Worldvu Satellites Limited Satellite radiator panels with combined stiffener/heat pipe
GB2587716A (en) 2018-04-26 2021-04-07 Yupo Corp Stretched porous film and film for printing

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5842226A (en) * 1981-09-07 1983-03-11 Nec Corp Manufacturing device for plasma semiconductor

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4226897A (en) * 1977-12-05 1980-10-07 Plasma Physics Corporation Method of forming semiconducting materials and barriers
JPS6032972B2 (en) * 1977-12-09 1985-07-31 株式会社日立製作所 Etching device
JPS5841658B2 (en) * 1979-06-15 1983-09-13 パイオニア株式会社 dry etching equipment
US4342901A (en) * 1980-08-11 1982-08-03 Eaton Corporation Plasma etching electrode
JPS6037118A (en) * 1983-08-08 1985-02-26 Semiconductor Energy Lab Co Ltd Plasma vapor phase reaction method
JPS6037119A (en) * 1983-08-08 1985-02-26 Semiconductor Energy Lab Co Ltd Plasma vapor phase reaction device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5842226A (en) * 1981-09-07 1983-03-11 Nec Corp Manufacturing device for plasma semiconductor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0620976A (en) * 1983-08-08 1994-01-28 Semiconductor Energy Lab Co Ltd Plasma vapor phase reactor and plasma vapor phase reaction method
JP2564748B2 (en) * 1983-08-08 1996-12-18 株式会社 半導体エネルギー研究所 Plasma vapor phase reaction apparatus and plasma vapor phase reaction method
JPH05144595A (en) * 1991-11-22 1993-06-11 Semiconductor Energy Lab Co Ltd Plasma processing device
JPH06140347A (en) * 1993-05-13 1994-05-20 Semiconductor Energy Lab Co Ltd Plasma vapor growth reaction method
JP2564753B2 (en) * 1993-05-13 1996-12-18 株式会社 半導体エネルギー研究所 Plasma gas phase reaction method

Also Published As

Publication number Publication date
JP2564748B2 (en) 1996-12-18
JPH0620976A (en) 1994-01-28
JPH0546094B2 (en) 1993-07-13

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