JPS6037041A - Data processor - Google Patents

Abstract

PURPOSE:To avoid a runaway without adding any external circuit by storing an instruction which resets the actuation of a data processor to its starting time point into an unused area of a memory which stores the instruction. CONSTITUTION:The instructions to reset the RAM clear actions are stored to all addresses of an unused area 22 of an ROM2. Thus a data processor is reset to its starting point even in case the area 22 is designated by an abnormal phenomenon. As a result, a CPU1 can perform a normal sequential operation after the action is restarted even though the abnormal action is temporary.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a data processing device having a protection function against runaway.

[Prior art]

Data processing devices are adapted to perform sequential operations in accordance with instructions stored in memory. When this device is used on a commercial power source, there is no problem as the voltage is stable, but when it is installed in a vehicle, etc., it may cause unexpected abnormal operation when the power supply voltage drops significantly, resulting in a runaway state. , in this case, the sequential operation becomes completely random. Various proposals have been made to prevent this from happening, but they have had the disadvantage of requiring a complicated external circuit, resulting in poor economic efficiency and reliability.

[Object and structure of the invention]

Therefore, an object of the present invention is to provide a data processing device that can prevent runaway without reducing economy and reliability.

In order to achieve this object, the present invention stores an instruction for returning the device to the operation at the start of operation in an unused area of the memory in which the instruction is stored. Hereinafter, the present invention will be described in detail using drawings showing embodiments.

〔Example〕

FIG. 1 is a block diagram showing an example of a data processing device. In the same figure, 1 is the CPU, 2 is the ROM, 13 is the RAM,
4 is an input/output device. After the device configured as described above is supplied with power, it performs step 100 as shown in FIG.
A "power-on reset" is performed at the time, and the operation starts. Thereafter, each time an instruction stored in ROM2 is read out, the CPU clears the rRAM in step 101 according to the read out instruction, as shown in FIG.
, "initial value setting" in step 102, etc. are performed one after another.

In this case, as shown in FIG. 3, the ROM 2 has an area 21 in which a program in which sequential operations of the CPU are written is stored, and an area 22 which is an unused area in which no program is stored. For this reason, the CPUI
1 is specified, and when the program stored there is read out, operations are performed in a predetermined order one after another. However, when the area 22 is designated due to an abnormal operation, since no program has been written there, the operation of the device after that point is no longer guaranteed.

Therefore, the present invention provides that all the addresses in area 22, which is an unused area of ROM 2, are stored in step 101 shown in FIG.
A command to return to the "rRAM clear" operation is stored.

In this way, if the area 22 is designated due to an abnormal phenomenon, the device returns to the state at the start of operation. Therefore, although in the past, the device could not perform normal sequential operations even if the abnormal operation was temporary, according to the present invention, it is possible to perform normal sequential operations after restarting the operation.

〔Effect of the invention〕

As explained above, the data processing device according to the present invention includes:
Since the command to return to the operation at the start of the device operation is stored in an unused area of the memory, there is no need to add an external circuit to prevent runaway, improving both economy and reliability, and preventing abnormal operation. If it is temporary, it has the effect that the normal sequential operation can be returned to after the operation is resumed.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an example of a data processing device, Figure 2 is a block diagram showing an example of a data processing device.
The figure is a flowchart showing the operation of the apparatus of FIG. 1, and FIG. 3 is a memory up. 1 ・ ・ ・ -CPU, 2 ・ ・ Φ R
OM, 3・0・@RAM, 4・ΦFist・I/O device. Patent applicant: Koito Manufacturing Co., Ltd. Agent Masaki Yamakawa (1 person)

Claims (1)

[Claims] 1. A data processing device that processes data according to instructions stored in a memory, characterized in that an unused area of the memory stores an instruction for returning to the operation at the time the device started operating.