JPS6036640B2 - traffic signal control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a traffic signal control device, and more particularly to a traffic signal control device having a function of skipping a predetermined display step of a traffic signal lamp according to traffic conditions. be.

For example, when the display of a traffic signal light comes to the step of allowing a right-turning vehicle to turn, if a vehicle detector detects that there is no right-turning vehicle, the step of allowing the right-turn is skipped and the system moves to the next step. However, efforts are being made to streamline traffic control. However, in order to reduce the size of the traffic signal control device and further reduce the number of assembly steps, it is advantageous to use 1.

However, in a traffic signal control device using an LSI, the operation of skipping a predetermined step cannot be performed in the same manner as in a conventional traffic signal control device that does not use 1. This invention was made in consideration of the above problem, and its purpose is to skip a predetermined step under a predetermined condition in a traffic signal control device using an LSI, and to make the skipped step When this occurs, the display of the traffic light is immediately switched to the next step after the skipped step, and the step counter is incremented at high speed to become extremely short, and the step counter advances to the next step after the skipped step within the time. An object of the present invention is to provide a traffic signal control device.

In order to achieve the above object, the present invention uses an LSI that includes at least a time counter and a step counter in a traffic signal control device, and includes a skip selection circuit that generates a signal under certain conditions in a skip step, and a skip selection circuit that generates a signal under certain conditions in a skip step. The above gate circuit adds a clock pulse faster than the normal clock pulse to 1 while the selection circuit signal is occurring, and the number of the next step to be skipped while the skip selection circuit signal is occurring. A data setting device that generates a signal, and when the signal of the skip selection circuit is not generated, it is controlled by the signal of the step counter of the upper 4SI, and when the signal of the skip selection circuit is generated, it is controlled by the signal of the data setting device. and a signal lamp control circuit to be controlled.

With the above configuration, the time counter, step counter, and other control circuits of the melon 1 are normally operated by ordinary circuits.

The step counter generates a step command signal at predetermined time intervals and applies it to the signal lamp control circuit, thereby causing the display step of the signal lamp to advance each predetermined time interval, but e.g. to skip it. Assume that the step allows a right-turning vehicle to turn right, and in this step, certain conditions are met, such as when a vehicle detector detects that there is no vehicle attempting to turn right, or when there is a request from a pedestrian. When a condition is met, such as when the time is over, or during a certain period, the skip selection circuit generates a signal, and by generating this signal, the signal set in the data setting circuit is added to the signal lamp control circuit. , the signal lamp control circuit directly switches the display of the signal lamp to the next step of the step that should be skipped, and a clock pulse faster than the normal clock pulse is applied to the LSI, so that the control circuit in Melon 1 operates at high speed. However, especially when the time counter is inputted with a high-speed clock pulse, the timekeeping operation becomes high speed, and therefore the step counter is shortened and a time step command signal is generated to command the next step after the skipped step. Therefore, the signal of the skip selection circuit disappears, after which the signal lamp control circuit is controlled by the signal of the step counter. In this way, when a certain condition is met for a step to be skipped, the display on the signal lamp is immediately switched to the next step after the step to be skipped, and the step counter advances at high speed to quickly restart the step. A signal is generated to command the next step of the skip step, and thereafter the signal lamp control circuit is controlled by the step counter, and the skip operation is performed regardless of the length of the set time of the skipped step. Although it is extremely short, it is carried out within a certain period of time, and the subsequent control of the signal lamps is carried out normally with almost no effect due to the skipping. Embodiments illustrating the present invention will be described in detail below.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention, in which 1 is an LSI, 2 is a time counter, 3 is a step counter, 4 is a timer, and counters 2, 3 and timer 4 are other components. LSI along with a control circuit (not shown)
It is built into I.

5 is a clock pulse generator, 6 is a divider which receives the clock pulse from the generator 5 and divides it into, for example, 1/1000, and 7 is an inhibit gate which receives the output of the frequency divider 6 as an input. , is an OR circuit that takes the output of gate 7 as one input,
The output of the OR circuit 8 is applied to the LSII and used as a timing pulse for its control circuit, and is also applied to the time counter 2 and timer 4.

9 is a decoder to which the output of step counter 3 is input;
1 is a skip selection circuit, 11 is a matrix circuit, and a decoder 9 instructs the steps of step counter 3;
The evolution signal is decoded and output through output lines Z, 6, and input into the pinboard matrix circuit 11.

In the matrix circuit 11, the time of each step of the display of the signal lamp device is set. The skip selection circuit 10 is a pin board, and is connected to the output line corresponding to the number of the step to be skipped by a pin, and outputs the output. In Figure 1, it is connected to output lines 5 through 8 with pins. In this embodiment, it is assumed that outputs are generated on output lines 5 to 8 in the step of permitting a right-turning vehicle to turn right. The output of the time counter 2 is added to the pinboard matrix circuit 11, and the output of the matrix circuit 11 is applied to the OR circuit 1.
2 to the step counter 3 and timer 4 as a reset input. Reference numeral 13 denotes a band circuit that outputs a signal extracted through the output line L' of the skip selection circuit 10 and a vehicle detection diagram (not shown).

) output signal 2D is input. The output of the AND circuit 13 is used as a prohibition input of the prohibition gate 7, and is also used as an input of the AND gate 14, the inverter 5, the gate 16, and the inverter 22. The clock pulse from the generator 5 is also input to the AND gate 14;
The output is input to the OR circuit 8. 17 is a data setting circuit, 18 is a storage circuit, data indicating the number of the next step after the skipped step is set in the data setting circuit 17, and when the gate 16 is open, this data is stored in the storage circuit 18. can be placed in

19 is a gate, 20 is a signal lamp control circuit, gate 19
By opening, the memory contents of the memory circuit 18 are transferred to the control circuit 2.
It can be set to 0.

Reference numeral 21 denotes a gate, and when the gate 21 is opened, the output of the step counter 3 is input to the control circuit 20.

The output of the inverter 15 is used as a reset input of the memory circuit 18. The output of the inverter 22 is used as an inhibit input of the gate 19, an input that opens the gate 21, and a set input of the flip-flop 23. Reference numeral 24 denotes an inverter, which receives the output of the timer 4 as an input, and outputs the output from the inverter 24 as a reset input of the flip-flop 23.

The output of timer 4 is also used as a trigger input for storage circuit 18. The reset output of flip-flop 23 is connected to inverter 2.
It is input to the OR circuit 12 via 5. Next, the operation will be explained.

In steps other than the skipped step, no output is generated on the output line L' of the skip selection circuit 10, and therefore there is no output from the AND gate 13, so the gate 7 is not inhibited, and the AND gate 14 is opened. It's not clear.

Therefore, the clock pulse generated by the clock pulse generator 5 is divided by a factor of 1,000 by the frequency divider 6 and applied to the LSII via the gate 7 and the OR circuit 8. The time counter 2 receives this clock pulse, counts the time, and inputs the time value to the matrix circuit 11. The step counter 3 generates a step command signal, which is sent to the decoder 9.
The signal is decoded and added to the matrix circuit 11.
Assuming that the step counter 3 is now at the first step, and therefore a signal instructing the first step is generated from the output line of the decoder 9, this decoded signal is applied to the matrix circuit 11, and the matrix The circuit 11 receives the time measurement output from the time counter 2 and generates a signal when the time set for the first step has elapsed, and this signal is input to the step counter 3 via the OR circuit 12. advance. Each time for each step is set in the matrix circuit 11, and every time the set time of the step commanded by the step counter 3 elapses, a signal is generated to increment the step counter 3. When the step counter 3 increments and produces a signal commanding the second step on output line 2 of the decoder 9, this signal is applied to the matrix circuit 11, which is set for the second step. As the time elapses, a signal is generated to increment the step counter 3, and this operation is repeated to advance the display step of the signal lamp. The timer 4 operates as if the output signal of the OR circuit 12 is generated and produces an output for a certain period of time, and this output is applied to the memory circuit 18 as a trigger, but since the output of the AND gate 13 is not present, the gate 16 is not open. Since there is no data setting circuit 17, the data in the data setting circuit 17 cannot be input to the storage circuit 18.
When the step counter 3 further increments and a signal instructing the fifth step is generated on the output line 5 of the decoder 9, a signal is generated on the output line L of the skip selection circuit 10, and the AND gate 13 is opened.

Assuming that the fifth to eighth steps are steps for permitting a right-turning vehicle to turn right, if the vehicle detector does not generate a signal 2D indicating that there is no right-turning vehicle, the output of the AND gate 13 will not exist. , therefore the fifth
In the step as well, as the time for the fifth step set in the matrix 11 elapses, the step counter 3 increments and generates a signal instructing the sixth step.
When the signal 2D is not present in the sixth to eighth steps, these steps are also controlled by the time set in the matrix circuit 11. Furthermore, and gate 1
When the output of No. 3 does not exist, the input of the inverter 22 does not exist (hereinafter, the absence of input or output is referred to as "L").
” indicates.

) Therefore, the output exists and the gate 21 is opened because the output is "H" (hereinafter, the presence of the output is indicated by "H"), and the step command signal of the step counter 3 is A signal lamp control circuit 201 is added through the control circuit 21, and the display of the signal lamp is controlled by the step command signal of the control circuit 20'.
When a command signal is generated and an output signal is generated on the output line L of the step selection circuit 10, when the signal 2D is present, the output of the AND gate 13 is present, and the gate 7 is inhibited by this output. The output of the frequency divider 6 is no longer applied to the LSII.

On the other hand, the AND gate 14 is opened by the output of the AND gate 13, and the clock pulse generated by the clock pulse generator 5 is passed through the gate 14 and the OR circuit 8 without passing through the frequency divider 6.
time counter 2 also joins the LSII via generator 5
No Ku. The clock pulse can be applied undivided. Assuming that the frequency divider 6 was dividing the clock pulse from the generator 5 by 1/1000, the clock pulse from the generator 5 was now directly applied to the time counter 2, timer 4, etc. in the LSII. At that time, the timekeeping speed will be 1,000 times faster than before. When the output of AND gate 13 becomes "H", this output "H" is applied to gate 16 and opens it.

Further, when the step counter 3 advances to the fifth step, an output is generated from the timer 4, and this output is sent to the A memory circuit 1.
8 as a trigger input. Therefore gate 16
By opening, the data set in the data setting circuit 17 can be input into the storage circuit 18. At this time, since the output of the AND gate 13 is ``H'', the output of the inverter 22 is ``L'', so the gate 21 is not opened and the gate 19 is not inhibited. The command signal is not input to the control circuit 20, but the data stored in the memory circuit 18 is input to the control circuit 2 through the gate 19. or 8th
Therefore, data indicating the next step, that is, the ninth step, is set, and this data is stored in the memory circuit 18 and input to the two control circuits. Therefore, the control circuit 2 switches the display of the signal light device to the ninth step. This operation is performed immediately when the step counter 3 advances to the fifth step and the command signal is generated, and the fifth step is skipped and the eighth step is skipped.
On the other hand, timer 4 receives clock pulses directly from clock pulse generator 5, and this clock pulse is 1,000 times faster than frequency divider 6.

When the output of frequency divider 6 is applied, timer 4 is operated by the output of OR circuit 12 and produces an output for, for example, 16 milliseconds. However, when clock pulses are applied directly from the generator 5, the output will be produced for only one thousandth of 16 milliseconds when activated. This output is applied to an inverter 24, and the output of the inverter 24 is used as the reset input of the flip-flop 23. The operation of the flip-flop 23 is shown in the table below.

In other words, set input S and set input R are both '
If it is 'L', both set output Q and reset output Q are 'H', and if set input S is 'L', reset input R is 'L'.
If is "H", the set output Q is "H" and the reset output Q is "L".

The set output and reset input are “H” and “L” respectively.
”, the set output and reset output are both “L”
, "H'1", and if both inputs are "H", no change in the output occurs.
As shown in the figure, when the step counter 3 increments from the fourth step to the fifth step, if the signal 2D exists, the output of the AND circuit 13 becomes "H" and the output of the inverter 22 is becomes “L”.

The output of the inverter 22 is used as a set input of the flip-flop 25. . Further, the output of the timer 4 becomes "H" for -1000th of 16 milliseconds, and therefore the output of the inverter 24 becomes "L" during that period. At this time, the reset output Q of the flip-flop 23 is "H", and the output of the inverter 25 becomes "L". When one thousandth of 16 milliseconds has elapsed, the output of the timer 4 becomes "L" and the output of the inverter 24 becomes "H".

At this time, the output of the inverter 22 remains "L", so the reset output Q of the flip-flop 23 becomes "L", and therefore the output of the inverter 25 becomes "H".
This output "H" is applied to the step counter 3 via the OR circuit 12 to advance it to the sixth step, and is also applied to the timer 4 to operate it. The output becomes "H" for one thousandth, the output of the inverter 24 becomes "L", the reset output Q of the flip-flop 23 becomes "H", and therefore the output of the inverter 25 becomes "L".16 When one thousandth of a millisecond has passed and the output of the timer 4 becomes "L", the output of the inverter 24 becomes "H" as before, the reset output Q of the flip-flop 23 becomes "L", Inverter 2
The output of the timer 5 becomes "H", the step counter 3 is incremented to the seventh step, and the output of the timer 4 becomes "H".

By repeating this operation B, the step counter 3 advances to the 9th step, and when a command signal appears on the output line 9 of the decoder 9, the output on the output line L of the step counter 0 disappears, and the AND gate is activated. 13 closes and its output disappears. After this time, B step counter 3
The control circuit 20 returns to the same operation as described for the first step and the second step, and the control circuit 20 controls the signal lamp according to the command signal from the step counter 3. When the output of the AND gate 13 disappears, the AND circuit 14 closes and the gate 7 opens, and the clock pulse divided by the frequency divider 6 is applied to the LSII, and the output of the inverter 22 becomes "H". Gate 21 opens and gate 19
is prohibited, the command signal of the step counter 3 is applied to the control circuit 20, and the output of the inverter 22 becomes "H", so that the output of the inverter 24 becomes "L" while the output of the timer 4 is present. As shown in the table, the set output of the flip-flop 23 becomes "L" and the reset output becomes "H", and when the output of the timer 4 is not present, both the outputs of the inverters 22 and 24 become ``H''. ', and in this case, no change occurs in the state of the flip-flop 23, and the set output remains at "L" and the reset output remains at "H". Therefore, the output of the inverter 25 remains at "L", and the step counter 3 receives a step signal only from the matrix 11. When the step counter 3 increments to the 9th step, the control circuit 2 switches the display of the signal lamp to the 9th step, and then the 9th step time set in the matrix 11 elapses. When a command signal is issued from the step counter 3, the control circuit 2 switches the display of the signal lamp to the tenth step. In the above explanation, the signal applied to the AND gate 13 is the signal when the vehicle detector detects the absence of a right-turning vehicle, but this may also be a signal issued in response to a pedestrian's request, or a constant For example, the signal may be a signal that occurs during a predetermined time period of a day.

Furthermore, although the step selection circuit 1 has selected the fifth to eighth steps, these steps can be arbitrarily selected, and the number of steps can also be arbitrarily selected.
In the embodiment shown in FIG. 1, a timer 4, a flip-flop 23, and an inverter 25 are provided, but the flip-flop 23 and inverter 25 are not necessarily required. If flip-flop 23 and inverter 25 are not provided, flip-flop 23 and inverter 25 do not generate step signals. On the other hand, the matrix circuit 11 is always operating, and when a high-speed clock pulse is applied to the LSII from the generator 5, the time counting speed of the time counter 2 increases by a thousand times.
The set time of the matrix circuit 11 is measured at a speed of a thousand times the sum. Therefore, during skip steps 5, 6, 7, and 8, each set time is equivalent to being shortened by one thousandth, and the output signal of the matrix circuit 11 causes the step counter 3 to shorten the set time by one thousandth. It advances in time and reaches the ninth step. Even when the flip-flop 23 is provided, the matrix circuit 11 continues to operate, but since the signal output from the flip-flop 23 is faster than the signal generated from the matrix circuit 11, the step counter 3
is stepped by the output signal from flip-flop 23. As explained above, according to the present invention, by using the traffic signal control device 1, the size of the device can be reduced and the assembly work can be simplified, and furthermore, certain conditions are met in the skipped steps. If the step is satisfied, immediately after switching to the skipped step, the display of the signal lamp will be switched to the skipped step,
By applying a clock pulse faster than normal to the time counter 2 in the mountain 11, the step counter 3 is caused to increment at a high speed and very quickly advances to a predetermined step, that is, the step next to the skipped step. It will be done.

Furthermore, according to the present invention, depending on the presence or absence of the condition signal 2D, it is possible to start skipping or stop skipping even when the step counter output is already in the skip position. It will also be possible to do so. Furthermore, if a flip-flop 23 is added as shown in the embodiment, a high-speed clock pulse is applied to the timer 4, so that regardless of the set time length of the skipped step, the time is always within a constant sum, that is, as shown in FIG. As shown, the step counter 3 is incremented to the next step after the skipped step within a time period obtained by multiplying the operating time of the timer 4 by the number of skipped steps. Skipping in this way does not affect the control of subsequent steps.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is an operational diagram. 1. ... LSI, 2 ... Time counter, 3.
...Step counter, 5...Clock pulse generator (second clock pulse generator), 6...
・Clock pulse divider (first clock pulse generator), 10...Skip selection circuit, 13, 14.
. . . AND gate, 17. . . Data setting device, 20 . . . Signal lamp control circuit. Figure 2 Figure 1

Claims (1)

[Claims] 1. A clock input terminal, a time counter that increments a clock introduced from the clock input terminal, an output terminal of a ticking time counter, a step increment input terminal, and a step counter that increments by a signal from the step increment input terminal. a skip selection circuit that generates a signal in the skipped step set by the setting means; a first gate circuit that outputs a skip signal based on the AND of the skip signal and a predetermined condition signal; By applying a normal clock pulse to the clock input terminal to increment the time counter at a normal speed while the first gate circuit is not generating a skip signal, thereby incrementing the step counter at a normal speed. While the step counter is incremented at a normal speed, while a skip signal is being generated from the first gate circuit, a clock pulse faster than a normal clock pulse is applied to the clock input terminal to increment the time counter at a high speed. a second gate circuit that increments the step counter at high speed; and a second gate circuit that indicates the number of the next step after the skipped step set by the setting means while the skip signal is generated from the first gate circuit. a data setting device that generates a signal; and a data setting device that is controlled by a signal from a step counter of the LSI when a skip signal is not generated from the first gate circuit, and that controls the data when a skip signal is generated from the first gate circuit. A traffic signal control device comprising a signal lamp control circuit controlled by a signal from a setting device.