JPS6036616B2 - Complex buffer memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a buffer memo in an information processing device.

In information processing devices, it has become common to employ a buffer memory method as a means of speeding up memory access.

The present invention provides a means for increasing the usage efficiency of this buffer memory. In the past, consideration has been given to improving the usage efficiency of the buffer memory by improving the correspondence with the main memory, but in the following cases, the capacity of the buffer memory may not be enough to improve the usage efficiency. decide.

That is, MVCL (MoveCharacter, L
When data with a long operand length is moved, such as in the case of an instruction such as .on), it is rare for the data to be moved to exist in a buffer memory, so data is frequently transferred from the main memory to the buffer memory.

As a result, the data stored in the buffer memory will be evicted. On the other hand, in the command following the MNCL command, M
The movement data of VCL instructions is rarely used, resulting in lower buffer memory utilization. M
The operand of the yCL instruction is transfer to the 1/0 buffer area, etc., and the operand length may be as long as 12,000 bytes in some cases. In this way, when reading data from the main memory that will never be used by the processing unit again, it is conceivable not to write it to the buffer memory, but the operands of the MNCL instruction are continuous as addresses. In order to sequentially process operands that are continuous as addresses, performance will deteriorate unless there is a buffer with the capacity of at least the registration unit (block) of the buffer memory.

That is, if the memory reference unit of the processing device is 8 bytes and the buffer memory block is 32 bytes, then
It is necessary to ensure that the main memory is referenced once every four times. In order to meet this requirement, the buffer memory of the present invention has a large capacity buffer memory and a small capacity buffer memory, and for example, the small capacity buffer is used for operand logic of the MNCL instruction.

In addition, programs that are used infrequently and have few loops should be saved so as not to use large buffers. Can be specified in grams. Related Buffer Memo There are examples in which two or more buffer memories are combined, one of which is a combination of an instruction-dedicated buffer memory and an operand-dedicated buffer memory. Another method is to temporarily store evicted blocks in a set-associative buffer memory in order to correct imbalances in the frequency of use of columns.

A feature of the present invention is that a large capacity buffer and a small capacity buffer can be used freely. An embodiment of the present invention will be described with reference to the drawings.

The designation of whether to use the large-capacity buffer memory or the 4-capacity buffer memory can be automatically detected by hardware or specified by a program.

In the former case, when the operand length of the MVCL instruction is 102 cores or more, or when the operands are discontinuous and have a large spread in a certain firmware instruction or scientific calculation loop processing (FORTRAN DO loop), the instruction The buffer switching flip-flop 13 is set to 1 at the start of execution, and when the process ends, the buffer switching flip-flop 13 is set to 0, and the large capacity buffer is used again. Buffer memory assignment control The buffer memory assignment address is set in the address register ARI by the CPU.

Bits 20 to 26 of ARI are input to addresses in address array 3 of a large-capacity buffer memory, and output data from address array 3 is compared with bits 8 to 19 of AR in comparator circuit 4, respectively. All rows 31-3
If there is no match in 4, the output of the OR circuit 17 becomes 0.
If a match is found in any one of the rows, it is output to the data bus line 23 of the buffer memory 5 of that row. On the other hand, the address array 6 of the small capacity buffer memory 8 is made up of registers, and is always fixed on one input C2 side of the comparator circuit 7.

Therefore, when output bits 8 to 26 of the ARI are determined to be the other CI of the comparison circuit 7, either one of the comparison circuits 7 will match, or both of them will not match. If there is no match, the output of the OR circuit 18 becomes 0. If a match is found, the data in the small capacity buffer memory 8 is transferred to the bus line 24.
is output to. Depending on the state of the buffer switching flip-flop 13, the BS output data is transferred to the AND circuits 14 and 1.
5 and the OR circuit 16, and sent to the instruction issue buffer IBR or operand read buffer OBR.

Also, whether there is data in the buffer memory or not,
After the switching of the buffer memory is controlled by the AND circuits 19 and 20 and the OR circuit 21, it is output to the Noti ruddermachifer signal 26. Write control of the buffer memory When no data is sent to the buffer memory, data from the MS (main memory) is sent to the data register DR2 and written to the block of the buffer memory.

Replacement of the small capacity buffer memory is determined by a replacement flip-flop 12. A store request from the CPU is subject to address control in the same way as a proposal request from the CPU, and write data is sent to DR2.
Writes to the block of the buffer memory with the match. o Buffer cancel operation The cancel address is sent from the channel or other CPU, set in ARI, and written to both the large capacity buffer and the small capacity buffer. The address array is compared and if a match is found, the block is invalidated.

Although the present invention has been described with reference to a set-associative large-capacity buffer memory of 128 columns x 4 rows and an associative-type small-capacity buffer memory, the specifications regarding the capacity can be easily changed.

According to this invention, the following effects can be obtained.

1. Since instructions and operands that are unlikely to be used again are operated using a small capacity buffer memory, the efficiency of using the large capacity buffer increases and the processing capacity of the processing device is improved.

2. Small-capacity buffers can use elements that can perform writing and writing at the same time, so when writing from the main memory to the buffer memory, it is possible to overlap writing at the same time. .

For this reason, NotinB issues data and commands in advance.
Even if it becomes Mfer, there is little performance deterioration. Since large-capacity buffers are implemented using IC memories, it is difficult to issue and write data at the same time. For this reason, NotinBu
When a mer occurs and data is being written from the main memory to the buffer memo, a read request from the processing device is forced to wait, reducing processing performance.

[Brief explanation of the drawing]

The figure is a block diagram showing one embodiment of the present invention.・1; Address register, 2
; Data register, 3; Large capacity buffer address array (28 columns x 40 columns), 4: Large capacity buffer comparison circuit, 5; Large capacity buffer memory section (1 total B) 6: Small capacity buffer associate Eve Regis, 7: Comparison circuit of small capacity buffer, 8; Memory part of small capacity buffer, 9
; Small capacity buffer validity bit control circuit, 10; Small capacity buffer replacement control circuit, 11; Small capacity buffer validity flip-flop, 12; Small capacity buffer replacement flip-flop, 13: Buffer switching flip-flop, 14 , 15, 19, 20;
AND circuit, 16, 17, 18, 21: OR circuit, 22
, 27, 28: Negation circuit.

Claims (1)

[Claims] 1. Select which buffer memory to use, a large-capacity buffer memory or a small-capacity buffer memory that stores infrequently used instructions and operands, depending on the type of instruction and/or the specifications of the operands specified in the instruction. A composite buffer memory characterized by having means for separating.