JPS6035647U - display device - Google Patents

display device

Info

Publication number
JPS6035647U
JPS6035647U JP12696383U JP12696383U JPS6035647U JP S6035647 U JPS6035647 U JP S6035647U JP 12696383 U JP12696383 U JP 12696383U JP 12696383 U JP12696383 U JP 12696383U JP S6035647 U JPS6035647 U JP S6035647U
Authority
JP
Japan
Prior art keywords
display section
reception
numerical value
sub
reception channels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12696383U
Other languages
Japanese (ja)
Inventor
稲田　光治
Original Assignee
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニー株式会社 filed Critical ソニー株式会社
Priority to JP12696383U priority Critical patent/JPS6035647U/en
Publication of JPS6035647U publication Critical patent/JPS6035647U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一例の構成図、第２図〜第４図はその
説明のための図、第５図は他の例の構成図である。 １は主表示部、２は副表示部、３はマイクロコンピュー
タ、４は受信ダイアル、７はチューナ、３１は中央処理
回路、３３はリードオンリーメモリ、３６．３７は表示
駆動回路である。FIG. 1 is a block diagram of one example of the present invention, FIGS. 2 to 4 are diagrams for explaining the same, and FIG. 5 is a block diagram of another example. 1 is a main display section, 2 is a sub-display section, 3 is a microcomputer, 4 is a reception dial, 7 is a tuner, 31 is a central processing circuit, 33 is a read-only memory, and 36 and 37 are display drive circuits.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 受信チャンネルを所定数ごとに表示する主表示部と、副
表示部とを有し、上記受信チャンネルを決定する定数を
記憶したリードオンリーメモリが設けられ、このリード
オンリーメモリには上記受信チャンネルの所定数ごとに
順次変化する数値が記憶され、受信ダイアルの回転に応
じて上記定数が読み出されると共に上記数値が読み出さ
れ、この読み出された上記数値に応じて上記主表示部を
駆動する手段と、上記受信チャンネルの所定数の範囲で
は上記受信ダイアルの回転に応じて上記副表示部を駆動
する手段とを有してなる表示装置。A read-only memory is provided, which has a main display section and a sub-display section that display reception channels in predetermined numbers, and stores constants that determine the reception channels. means for storing a numerical value that changes sequentially for each number, reading out the constant and the numerical value according to the rotation of the reception dial, and driving the main display section according to the read numerical value; , means for driving the sub-display section in response to rotation of the reception dial within a range of a predetermined number of the reception channels.
JP12696383U 1983-08-17 1983-08-17 display device Pending JPS6035647U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12696383U JPS6035647U (en) 1983-08-17 1983-08-17 display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12696383U JPS6035647U (en) 1983-08-17 1983-08-17 display device

Publications (1)

Publication Number Publication Date
JPS6035647U true JPS6035647U (en) 1985-03-12

Family

ID=30288518

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12696383U Pending JPS6035647U (en) 1983-08-17 1983-08-17 display device

Country Status (1)

Country Link
JP (1) JPS6035647U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5752218A (en) * 1980-09-11 1982-03-27 General Denshi Kogyo Kk Receiving frequency display device of radio receiver

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5752218A (en) * 1980-09-11 1982-03-27 General Denshi Kogyo Kk Receiving frequency display device of radio receiver

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