JPS6035541A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6035541A
JPS6035541A JP58144714A JP14471483A JPS6035541A JP S6035541 A JPS6035541 A JP S6035541A JP 58144714 A JP58144714 A JP 58144714A JP 14471483 A JP14471483 A JP 14471483A JP S6035541 A JPS6035541 A JP S6035541A
Authority
JP
Japan
Prior art keywords
stem
semiconductor device
semiconductor element
glass
window
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58144714A
Other languages
Japanese (ja)
Inventor
Seiichi Iwamatsu
誠一 岩松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP58144714A priority Critical patent/JPS6035541A/en
Publication of JPS6035541A publication Critical patent/JPS6035541A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To obtain an image sensor or an EP-ROM of low cost by assembling a semiconductor element into a plastic stem and bonding a plate of crystal, sapphire or glass for projecting a ray of light onto an element surface on the stem as a window. CONSTITUTION:A semiconductor element 12 is assembled on a plastic stem 11 composed of epoxy resin, a lead frame and etc. and said stem 11 is provided with a glass plate 13 bonded on the stem 11. Thus, a light irradiation properties are not deteriorated and it becomes possible to obtain the low-cost semiconductor device.

Description

【発明の詳細な説明】 従来、ガラス窓を通して元を照射して機能させる半導体
gtとして、イメージ寺センサー、BP−ROM等があ
り、これらの半導体装置は、通例セラミンク・ステムに
組立てられ、該セラミック・パンケージ上に石英番サフ
ァイヤ、またはガラス板を窓として貼付けているのが通
例であった。
[Detailed Description of the Invention] Conventionally, image sensors, BP-ROMs, etc. have been used as semiconductor devices that function by irradiating the source through a glass window, and these semiconductor devices are usually assembled on a ceramic stem and - It was customary to attach a quartz sapphire or glass plate to the top of the pan cage as a window.

しかし、上記従来技術ではセラミック・ステム等が高価
であるという欠点があった。。
However, the conventional technology described above has a drawback in that the ceramic stem and the like are expensive. .

本発明はかかる従来技術の欠点をなくし、安価なイメー
ジ・センサーやK P −ROMを提供することを目的
とする。
It is an object of the present invention to eliminate the drawbacks of the prior art and provide an inexpensive image sensor and KP-ROM.

上記目的を達成するための本発明の基本的な構成は、半
導体装置に於いて、半導体素子をプラスチック・ステム
に組立て、該半導体素子表面に光線を照射する為の石英
、サファイヤまたはガラス板を窓として、前記プラスチ
ック・ステム上に貼付けた事を特徴とする。
The basic structure of the present invention for achieving the above object is that, in a semiconductor device, a semiconductor element is assembled on a plastic stem, and a quartz, sapphire or glass plate is used as a window to irradiate the surface of the semiconductor element with light. It is characterized in that it is pasted on the plastic stem.

以下、実施例により本発明を詳述する。Hereinafter, the present invention will be explained in detail with reference to Examples.

第1図は、従来技術による半導体装置の断面図であり、
セラミンク拳ステム1には半導体素子2が組立てられ、
金属キヤツプ6に貼付けられたガラス板4が一体となり
、セラミンク、−ステム1に組立てられτ成る。
FIG. 1 is a cross-sectional view of a semiconductor device according to the prior art,
A semiconductor element 2 is assembled on the ceramic fist stem 1,
The glass plate 4 affixed to the metal cap 6 is integrated into a ceramic stem 1 to form τ.

第2口拡本発明による一実施例を示す半導体装置の断面
図でおり、エポキシ樹脂とリード・フレタ本等により構
成されたグラスチンク拳ステム11には半導体素子12
が組立てられ、前記グラスチンクφステム11にをよガ
ラス板15が貼付られて成る。
The second enlarged view is a sectional view of a semiconductor device showing an embodiment of the present invention, and a glass tink fist stem 11 made of epoxy resin, reed fleta, etc. has a semiconductor element 12.
is assembled, and a glass plate 15 is attached to the glass tink φ stem 11.

上記の如く、本発明によるグラスチック封止での窓形成
により光照射性能に於いて特に性能劣化する事もなく、
安価な半導体装置が提供できる効果がある。
As mentioned above, there is no particular deterioration in light irradiation performance due to window formation in glass sealing according to the present invention.
This has the effect of providing an inexpensive semiconductor device.

本Q明はイメージ・センサー、ライン拳センサー、太陽
電池、MP−ROM等の光?レーザー照射を用いる半導
体装置に応用することができる。
Q: Is the light of image sensor, line fist sensor, solar cell, MP-ROM, etc.? It can be applied to semiconductor devices that use laser irradiation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来技術による半導体装置の断面図を。 第2図は本発明の一実ノ膚例を示す半導体装置の断面図
である。 1・・・・・・セラミック拳スラム、11・・・・・・
フラスチノク・ステム、 2.12・・・・・・半導体
素子、5・・・・・・金属キャンプ、4.i5−・・・
・・ガラス板。 以 上 出願人 株式会社諏訪精工舎 第1図 ど 第2図
FIG. 1 is a cross-sectional view of a semiconductor device according to the prior art. FIG. 2 is a sectional view of a semiconductor device showing an example of the present invention. 1...Ceramic fist slam, 11...
Flastinok stem, 2.12... Semiconductor element, 5... Metal camp, 4. i5-...
...Glass plate. Applicant: Suwa Seikosha Co., Ltd. Figures 1 and 2

Claims (1)

【特許請求の範囲】 半導体素子をプラスチック・ステムに組立て。 該半導体素子表面に光線を照射する為の石英、サファイ
ヤまたはガラス板を窓として、前記プラスチック・ステ
ム上に貼付けた事を特徴とする半導体装置。
[Claims] A semiconductor device is assembled to a plastic stem. A semiconductor device characterized in that a quartz, sapphire or glass plate is pasted on the plastic stem as a window for irradiating a light beam onto the surface of the semiconductor element.
JP58144714A 1983-08-08 1983-08-08 Semiconductor device Pending JPS6035541A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58144714A JPS6035541A (en) 1983-08-08 1983-08-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58144714A JPS6035541A (en) 1983-08-08 1983-08-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6035541A true JPS6035541A (en) 1985-02-23

Family

ID=15368584

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58144714A Pending JPS6035541A (en) 1983-08-08 1983-08-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6035541A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5115299A (en) * 1989-07-13 1992-05-19 Gte Products Corporation Hermetically sealed chip carrier with ultra violet transparent cover

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5115299A (en) * 1989-07-13 1992-05-19 Gte Products Corporation Hermetically sealed chip carrier with ultra violet transparent cover

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