JPS6034096A - Thick film circuit and method of producing same - Google Patents

Thick film circuit and method of producing same

Info

Publication number
JPS6034096A
JPS6034096A JP14346383A JP14346383A JPS6034096A JP S6034096 A JPS6034096 A JP S6034096A JP 14346383 A JP14346383 A JP 14346383A JP 14346383 A JP14346383 A JP 14346383A JP S6034096 A JPS6034096 A JP S6034096A
Authority
JP
Japan
Prior art keywords
insulator
thick film
film circuit
conductor
lower conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14346383A
Other languages
Japanese (ja)
Inventor
宮本 興一
深沢 一夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ohkura Electric Co Ltd
Original Assignee
Ohkura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ohkura Electric Co Ltd filed Critical Ohkura Electric Co Ltd
Priority to JP14346383A priority Critical patent/JPS6034096A/en
Publication of JPS6034096A publication Critical patent/JPS6034096A/en
Pending legal-status Critical Current

Links

Landscapes

  • Laminated Bodies (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (a)、発明の属する技術分野 本発明は、厚膜回路及びその製造方法に関し1特に、厚
膜回路において回路内の導電路をクロスオーバする必要
がある場合におけるクロスオーバの構造及びそのクロス
オーバ構造を有する厚膜回路の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical field to which the invention pertains The present invention relates to a thick film circuit and a method for manufacturing the same.1 In particular, the present invention relates to a thick film circuit and a method for manufacturing the same. The present invention relates to a method for manufacturing a thick film circuit having a cross-over structure and a cross-over structure thereof.

(b)、従来技術の説明 厚膜回路において多層配線を行う場合には、下部導体と
下部導体の間にピンホールがなく、耐電圧の高い絶縁体
で、かつ上部導体の印刷性i=良好でめ9、絶縁体の縁
で該上部導体が断糾しない“造の厚膜回路が要求される
(b) Description of the prior art When performing multilayer wiring in a thick film circuit, there are no pinholes between the lower conductors, an insulator with high withstand voltage is used, and the printability of the upper conductor is good (i = good). 9. A thick film circuit is required in which the upper conductor does not break at the edge of the insulator.

従来におけるこの種の厚膜回路とその製造方法について
第1図〜第3図に沿って説明する。
A conventional thick film circuit of this type and its manufacturing method will be explained with reference to FIGS. 1 to 3.

第1図及び第2図に示すが如く、厚膜回路は以下の工程
によって製造される。即ち、先づ、絶縁基板1に下部導
体2及び下部導体2をはさんで下部導体3を印刷し、乾
燥、焼成する1次に該下部導体2上に絶縁体4を印刷踵
乾燥させる。絶縁体層の乾燥膜厚は約50〜60 pm
である。続いて、該絶縁体4上に上部導体5を印刷、乾
燥し、該絶縁体4と共に焼成する。
As shown in FIGS. 1 and 2, the thick film circuit is manufactured by the following steps. That is, first, the lower conductor 3 is printed on the insulating substrate 1 by sandwiching the lower conductor 2 and the lower conductor 2, and then dried and fired. Next, the insulator 4 is printed and dried on the lower conductor 2. The dry thickness of the insulator layer is approximately 50-60 pm
It is. Subsequently, the upper conductor 5 is printed on the insulator 4, dried, and fired together with the insulator 4.

又は別の方法として、第3図に示すが如く、絶縁基板1
に下部導体2及び下部導体2をはさんで下部導体3を印
刷し、乾燥、焼成する0次いで、該下部導体2上に絶縁
体4aを印刷し、乾燥する。
Or as another method, as shown in FIG.
Then, an insulator 4a is printed on the lower conductor 2 and dried.

再度、絶縁体4bを同一パターンマスクで印刷、乾燥し
、2層構造とする。絶縁体層の乾燥総厚は約50〜60
μmである。続いて、該絶縁体4b上に上部導体5を印
刷1、乾燥し、該絶縁体と共に焼成する。
The insulator 4b is printed again using the same pattern mask and dried to form a two-layer structure. The total dry thickness of the insulator layer is approximately 50-60
It is μm. Subsequently, the upper conductor 5 is printed 1 on the insulator 4b, dried, and fired together with the insulator.

上記2力法でけ絶縁体4又は4d%4bをそれぞれ印刷
、乾燥に留めておき、上部導体5を印刷、乾燥後に同時
に焼成しているが、それぞれ印刷、乾燥、焼成を繰り返
して多層配線をもされている。
In the two-force method, the insulator 4 or 4d%4b is printed and dried, and the upper conductor 5 is printed, dried, and fired at the same time, but the printing, drying, and firing are repeated to form multilayer wiring. It has also been done.

しかるに、上記従来の方法では、絶縁体層の厚さがかな
りらり、絶縁体の段差Eに起因して上部導体5の印刷性
が悪く、上部導体5の細り、かすれが発生し、しいては
断線を惹起する欠点があった。
However, in the above conventional method, the thickness of the insulator layer is quite large, and the printability of the upper conductor 5 is poor due to the step E of the insulator, and the upper conductor 5 becomes thinner and blurred. had the disadvantage of causing wire breakage.

上記欠点を除去する為に、従来、該上部導体5を2回連
続して印刷し、E部での導体のペースト量を増加させる
方法、あるいは該上部導体5を下部導体2.3より幅広
く設計する方法が試みられたりしていた。又、上部導体
を段差E部の箇所のみを幅広く設計する等の方法が採ら
れていた。
In order to eliminate the above-mentioned drawbacks, conventional methods include printing the upper conductor 5 twice in succession to increase the amount of conductor paste in the E section, or designing the upper conductor 5 to be wider than the lower conductor 2.3. Some methods were being tried. Also, a method has been adopted in which the upper conductor is designed to be wide only at the step E portion.

しかしながら、上記いずれの方法も有効な解決策とはな
らず、依然として本来の上記欠点が残っていたジ、ある
いはそれらの方法に起因する他の新しい欠点が派生した
ジしていた。
However, none of the above methods provided an effective solution, and either the original drawbacks described above still remained or other new drawbacks caused by these methods were derived.

(C)、発明の目的 本発明は従来の技術に内在する上記欠点を解消する為に
なされたものであり1従って不発明の目的は、多層配線
を行うに当り、絶縁体を形状、面積の具するパターンマ
スク2枚以上で印刷を2回以上行い、それにより階段状
の段差をもつ絶縁体を形成し、絶縁に十分な厚さを有し
、絶縁体の縁で上部導体の断線が発生しない新規な厚膜
回路及びその製造方法を提供することにある。
(C), Purpose of the Invention The present invention has been made to eliminate the above-mentioned drawbacks inherent in the conventional technology.1 Therefore, the purpose of the invention is to improve the shape and area of insulators when performing multilayer wiring. Printing is performed two or more times with two or more pattern masks, thereby forming an insulator with stepped steps, and having a thickness sufficient for insulation, causing disconnection of the upper conductor at the edge of the insulator. An object of the present invention is to provide a novel thick film circuit and a method for manufacturing the same.

(d)、発明の構成 上記目的を達成する為に、本発明に係る厚膜回路は、絶
縁基板上に形成された下部導体と、該下部導体上に形成
された少−なくとも2個の段差を有する階段状の絶縁体
と、該絶縁体上に形成された上部導体とを具備して構成
され、また本発明に係る厚膜回路の製造方法は、絶縁基
板上に下部導体を形成し、該下部導体上に少なくとも2
段の段差を有する階段状の絶縁体を少なくとも2種のパ
ターンマスクを用いてスクリーン印刷技術により形成し
、前記絶縁体上をこ上部導体を形成して多層配線を行う
ことを特徴とする。
(d) Structure of the Invention In order to achieve the above object, the thick film circuit according to the present invention includes a lower conductor formed on an insulating substrate, and at least two conductors formed on the lower conductor. The method for manufacturing a thick film circuit according to the present invention includes a stepped insulator having steps and an upper conductor formed on the insulator, and a method for manufacturing a thick film circuit according to the present invention includes forming a lower conductor on an insulating substrate. , at least two
The present invention is characterized in that a step-like insulator having steps is formed by screen printing using at least two types of pattern masks, and a conductor is formed on the insulator to perform multilayer wiring.

(e)、発明の詳細な説明 以下、本発明をその好ましい一実施例について図面を参
照しなから具体的に説明する。
(e) Detailed Description of the Invention Hereinafter, a preferred embodiment of the present invention will be specifically described with reference to the drawings.

第4図は本発明に係る厚膜回路の一実施例を示す要部(
クロスオーバ構造)平面図、第5図は第4図のb −b
’線に沿って切断し矢印の方向に見た断面図である。
FIG. 4 shows the main part (
Crossover structure) Plan view, Figure 5 shows b-b in Figure 4.
It is a sectional view taken along the line ' and viewed in the direction of the arrow.

第4図及び第5図において、参照番号lは絶縁基板を示
し、該絶縁基板1上にはy軸方向に下部導体2が、X軸
方向に原点を含む中間部分を除いて下部導体3がそれぞ
れ形成されている。下部導体2上には原点を中心として
絶縁体4c、4dが形成され、絶縁体4cと絶縁体4d
との間には階段状の段差Fか設けられている。絶縁体4
cs4d上には上部導体5が形成され、その両端部はそ
れぞれ下部導体3に接続・されている。
4 and 5, reference number l indicates an insulating substrate, on which a lower conductor 2 is disposed in the y-axis direction, and a lower conductor 3 is disposed in the x-axis direction except for the middle portion including the origin. each formed. Insulators 4c and 4d are formed on the lower conductor 2 with the origin as the center, and the insulator 4c and the insulator 4d
A step-like step F is provided between the two. Insulator 4
An upper conductor 5 is formed on the cs4d, and both ends thereof are connected to the lower conductor 3, respectively.

次いで本発明に係る厚膜回路の製造方法について説明す
るに、先づ、絶縁基板1上のX軸方向に下部導体2を、
X軸方向に原点を含む中間部分を除いて下部導体3をそ
れぞれ印・刷し、乾燥、焼成する。次に該下部導体2上
に第1のパターンマスクを用いて絶縁体4Cを印刷し、
乾燥させる。続いて上部導体が配線される方向に段差が
形成される様に、該絶縁体4C%即ち、上記第1のパタ
ーンマスクよりも面積が若干狭い第2のパターンマスク
を用いて絶縁体4dを該絶縁体4c上に印刷し、乾燥さ
せる。次に重ね印刷された該絶縁体4C14d上に下部
導体2とクロスして上部導体5を印刷して上部導体5の
両端をそれぞれ対応する下部導体2と接続し、乾燥させ
、同時に焼成する。
Next, to explain the method for manufacturing a thick film circuit according to the present invention, first, the lower conductor 2 is placed on the insulating substrate 1 in the X-axis direction.
The lower conductor 3 is printed, except for the middle portion including the origin in the X-axis direction, and then dried and fired. Next, an insulator 4C is printed on the lower conductor 2 using a first pattern mask,
dry. Next, the insulator 4d is patterned using a second pattern mask whose area is slightly smaller than the first pattern mask, that is, the insulator 4C%, so that a step is formed in the direction in which the upper conductor is wired. Print on the insulator 4c and dry. Next, an upper conductor 5 is printed on the overprinted insulator 4C14d, crossing the lower conductor 2, and both ends of the upper conductor 5 are connected to the corresponding lower conductor 2, dried, and fired at the same time.

上記実施例においては、工程低減の為に、上部導体5を
印刷して乾燥させた後に、絶縁体4c以後を同時に焼成
しているが、絶縁体4ON4d%上部導体5をそれぞれ
個別に焼成しても良い。この場合には全焼成回数が4回
となる。又、焼成回数を3回としてもよい。
In the above example, in order to reduce the number of steps, after printing and drying the upper conductor 5, the insulator 4c and subsequent parts are fired at the same time, but the insulator 4ON4d% upper conductor 5 is fired individually. Also good. In this case, the total number of firing times is four. Further, the number of firings may be three times.

また、上記実施例においては、2種類のパターンマスク
により2段の段差を有する絶縁体について説明したが、
3種類以上のパターンマスクを用いて3段階以上の段差
を設けることも可能である。
Furthermore, in the above embodiment, an insulator having two steps using two types of pattern masks was explained.
It is also possible to provide three or more steps using three or more types of pattern masks.

この場合にはピンホールの発生は指数関数的に減少する
効果が生ずる。
In this case, the effect is that the occurrence of pinholes is exponentially reduced.

更にまた、本実施例においては、X軸方向の長さのみが
異なl)y軸方向の長さが同じパターンマスクを用いて
絶縁体のX軸方向のみに段差を設けているが、y軸方向
の長さも異なる相似のパターンマスクを用いて絶縁体の
X軸方向のみならず、y軸方向にも段差を形成し一上部
導体を形成する場合に方向性を除去することも可能であ
る。
Furthermore, in this example, a step is provided only in the X-axis direction of the insulator using pattern masks that differ only in length in the X-axis direction and have the same length in the y-axis direction. It is also possible to eliminate directivity when forming the upper conductor by forming steps not only in the X-axis direction of the insulator but also in the y-axis direction using similar pattern masks with different lengths in the directions.

(f)、発明の詳細な説明 本発明は以上の如く構成され、作用するものであシ、本
発明によれば以下の効果が発生する。
(f) Detailed Description of the Invention The present invention is constructed and operates as described above, and the present invention provides the following effects.

即ち、本発明による上記方法によシ多層配線を行うこと
によって、下部導体と上部導体間にピンホールの発生が
なく、絶縁に十分な絶縁体が得られ、かつ絶縁体層の総
厚が関係せず、絶縁体の段差は、乾燥後で25〜307
7m、焼成を行えば20〜25μmと、従来よ#)2分
の1以下に押えられる。
That is, by performing multilayer wiring according to the above method according to the present invention, there is no generation of pinholes between the lower conductor and the upper conductor, sufficient insulation is obtained, and the total thickness of the insulation layer is No, the height difference of the insulator is 25~307cm after drying.
7 m, but by firing it can be reduced to 20 to 25 μm, less than half that of conventional methods.

更に大きな効果は、絶縁層の周辺に階段状の段差が形成
されるので、その上に形成される上部導体の印刷性は良
好であシ、従来における如く断線等の障害の発生が除去
され、不良率が著るしく低減される。又、耐電圧、断線
等の検査を必要としない利点が生ずる。
An even greater effect is that since a step-like step is formed around the insulating layer, the printability of the upper conductor formed thereon is good, and the occurrence of troubles such as disconnections as in the past is eliminated. The defective rate is significantly reduced. Further, there is an advantage that inspections for withstand voltage, disconnection, etc. are not required.

まだ、本発明によれば、上部導体の印刷時に段差Fで発
生するにじみが抑えられるから、上部導体の間隔を狭め
ることができ、その結果、配線密度を高めることが可能
となる。
Still, according to the present invention, since the bleeding that occurs at the step F when printing the upper conductor is suppressed, the interval between the upper conductors can be narrowed, and as a result, the wiring density can be increased.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来における多層配線厚膜回路の概略平面図、
第2図は第1図のa −a’線に沿って切断し矢印の方
向に見た断面図、第3図は従来における他の例の第2図
と同様の断面図、第4図は本発明に係る多層配線厚膜回
路の一実施例を示す概略平面図、第5図は第4図のb 
−b’線に沿って切断し矢印の方向に見た]断面図であ
る。 1・愉・絶縁基板、2.3Φ・・下部導体、4.4a、
4b、4c、4ds*e絶縁体、56.。 上部導体、E、F・・中段差部 特許出願人 大倉電気株式会社 代 理 人 弁理士 熊谷雄太部 第1 図 N2図 第3図 第4図 第5図
Figure 1 is a schematic plan view of a conventional multilayer wiring thick film circuit.
Fig. 2 is a sectional view taken along line a-a' in Fig. 1 and seen in the direction of the arrow, Fig. 3 is a sectional view similar to Fig. 2 of another conventional example, and Fig. 4 is a sectional view of Fig. 1. A schematic plan view showing an embodiment of the multilayer wiring thick film circuit according to the present invention, FIG.
FIG. 3 is a sectional view taken along line -b' and viewed in the direction of the arrow. 1.Insulating board, 2.3Φ...lower conductor, 4.4a,
4b, 4c, 4ds*e insulator, 56. . Upper conductor, E, F...middle level difference Patent applicant Okura Electric Co., Ltd. Representative Patent attorney Yuta Kumagai 1 Figure N2 Figure 3 Figure 4 Figure 5

Claims (2)

【特許請求の範囲】[Claims] (1)、絶縁基板上に形成された下部導体と、該下部導
体上に形成された少なくとも2段の段差を有する階段状
の絶縁体と、該絶縁体上に形成された上部導体とを具備
することを特徴とした厚膜回路。
(1) A lower conductor formed on an insulating substrate, a stepped insulator having at least two steps formed on the lower conductor, and an upper conductor formed on the insulator. A thick film circuit that is characterized by:
(2)、絶縁基板上Oこ下部導体を形成し、該下部導体
上に少なくとも2段の段差を有する階段状の絶縁体を少
なくとも2種のマスクを用いてスクリーン印刷技術によ
ジ形成し、前記絶縁体上に上部導体を形成して多層配線
を行うことを特徴とする厚膜回路の製造方法。
(2) forming a lower conductor on an insulating substrate, forming a stepped insulator having at least two steps on the lower conductor by screen printing technology using at least two types of masks; A method for manufacturing a thick film circuit, comprising forming an upper conductor on the insulator to perform multilayer wiring.
JP14346383A 1983-08-04 1983-08-04 Thick film circuit and method of producing same Pending JPS6034096A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14346383A JPS6034096A (en) 1983-08-04 1983-08-04 Thick film circuit and method of producing same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14346383A JPS6034096A (en) 1983-08-04 1983-08-04 Thick film circuit and method of producing same

Publications (1)

Publication Number Publication Date
JPS6034096A true JPS6034096A (en) 1985-02-21

Family

ID=15339288

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14346383A Pending JPS6034096A (en) 1983-08-04 1983-08-04 Thick film circuit and method of producing same

Country Status (1)

Country Link
JP (1) JPS6034096A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6284975U (en) * 1985-11-18 1987-05-30
JPH0193192A (en) * 1987-10-05 1989-04-12 Fujitsu Ltd Thick film multilayer interconnection substrate
JPH02110995A (en) * 1988-10-19 1990-04-24 Matsushita Electric Ind Co Ltd Thick film hybrid integrated circuit device
JP2015005049A (en) * 2013-06-19 2015-01-08 大日本印刷株式会社 Touch panel cover member and manufacturing method of the cover member

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5138256B1 (en) * 1969-05-19 1976-10-20
JPS5296356A (en) * 1976-02-10 1977-08-12 Tokyo Shibaura Electric Co Method of producing multilayer printed circuit board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5138256B1 (en) * 1969-05-19 1976-10-20
JPS5296356A (en) * 1976-02-10 1977-08-12 Tokyo Shibaura Electric Co Method of producing multilayer printed circuit board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6284975U (en) * 1985-11-18 1987-05-30
JPH0193192A (en) * 1987-10-05 1989-04-12 Fujitsu Ltd Thick film multilayer interconnection substrate
JPH02110995A (en) * 1988-10-19 1990-04-24 Matsushita Electric Ind Co Ltd Thick film hybrid integrated circuit device
JP2015005049A (en) * 2013-06-19 2015-01-08 大日本印刷株式会社 Touch panel cover member and manufacturing method of the cover member

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