JPS6034027A - Semiconductor device - Google Patents

Abstract

PURPOSE:To contrive to curtail the testing hours when the function of an LSI functional unit connected with input terminals and output fubbers of the plural number respectively is to be tested by a method wherein a control terminal is connected to the respective buffers in common, and a signal of (0) or (1) is supplied therefrom to the buffers. CONSTITUTION:Input terminals 11 and output buffers 21 of the plural number respectively are connected to an LST functional unit 10, and signals corresponding to input are outputted from the output terminals 23-26 of the respective buffers 21. When the function of the functional unit 10 thereof is to be tested, a control terminal 20 is connected in common to the respective buffers 21 previously, and a signal or (0) or (1) is supplied to the respective buffers. At this time, the level of the function of the terminal 20 is so set as to make when the signal is (0), outputs of the buffers 21 become also to (0), and when the signal is (1), outputs of the buffers 21 become also to (1). Accordingly, the number of times of the functional test is made so as to be completed by two times.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a control terminal that can control each output level.

In recent years, as the degree of integration of integrated circuits has improved and the scale has shifted from LSI to VLSI, general-purpose L
In addition to SI, the development of semi-custom LSI has become active. In particular, the development of LSIs designed using a gate array type, which is a type of semi-custom LSI, has become common. LS designed by this one-way gate array
I is attracting attention as a result of trends toward lower prices, smaller sizes, higher densities, higher reliability, etc. for digital devices.

Current digital devices are configured using a large number of general-purpose SSI/MSI and mounted on printed circuit boards, but it is possible to incorporate these SSI/MSI into an LSI designed using a gate array method. LSI technology is progressing.

As is well known, this one-gate array LSI is characterized by being developed by changing only the wiring process to a customer-specific circuit on a wafer that has undergone a diffusion process during the LSI manufacturing process. The advantages of this LSI for customers include low development costs, short development periods, confidentiality of design, ease of conversion into LSI, and the possibility of ordering in small quantities, while the advantages for LSI manufacturers include a reduction in development engineering man-hours. Possible, can be produced on the same line as mass production method, increases added value, etc.

An LSI designed using this gate array type has a variable number of input terminals and output terminals in order to realize a circuit according to customer specifications. Further, the number of output terminals of one circuit is not the same as the number of output terminals of another circuit, and the positions of the output terminals are also different, and the same is true of the input terminals. Furthermore, the circuit functions of customer specifications vary widely, and this LS
Functional testing of I is performed based on customer specifications, so testing of input/output terminals must be performed for each functional test, and the disadvantage is that the time required for functional testing of LSIs designed using a single gate array method is extremely large. was there.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that solves these drawbacks and significantly shortens the time required for functional testing.

The structure of the semiconductor device of the present invention is characterized in that it includes a plurality of output buffers whose respective output levels can be uniquely determined by an external signal supplied from one external control terminal.

The present invention will be explained in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the functions of a conventional LSI.

As shown in the figure, this LSI outputs signals from an LSI functional unit 10 connected to a plurality of input terminals 11 to output terminals 13 to 16 through four output buffers 12. Output terminals 13, 14, 15 by input cover turn from input terminal 11.

A "0" level or a "1" level is output to 16.

When measuring the levels of these output terminals, a certain input test pattern is used to test the "1" level of the output terminal 13 when the output terminal 13 reaches the "1" level.
When the output terminal 13 becomes a "0" level output due to another input cover turn, a "0" level test is performed. Similarly, output terminals 14 and 15.

16, each output level is measured by each input cover turn. The level of the output pin is determined by the specifications of this LSI unit 10, but according to this example, there are four output terminals, and their "1" level or "0" is used to measure the output level with the input test butter. Measuring the level requires a test pattern of 4 x 2 = 8 degrees on average, and has the disadvantage that it is time consuming as it is a functional test.

FIG. 2 is a block diagram illustrating the invention in detail. In this embodiment as well, a signal from an LSI functional unit (10) having a plurality of input terminals 11 is passed through four output buffers 21 to output terminals 23, 24, 25.

In this embodiment, a control terminal 20 connected to each output buffer 21 is provided. The functions of this control terminal 20 are 1. The design is such that when the control signal is "0", the output of the output buffer 21 is "0", and when the control signal is "1", the output of each output buffer sofa 21 is "1". . Therefore, the output terminals 23, 24, 2
When testing the "0" level of the output terminals 23, 24, 25, and 26, setting the level of the control terminal 20 to the "0" level allows measurement independent of the input test pattern. When testing the "1" level, set the control terminal 200 level to the "1" level to enable measurement. That is, by providing a control terminal, measurement of the output level of an LSI can be performed only two times.

This example shows the case where the number of output terminals is four, but considering the recent increase in the number of pins and high functionality of LSIs, the increase in the number of output terminals and the complexity of the functions make it difficult to measure the output level. The number of test patterns required is on average more than twice the number of output terminals, and the time required for functional testing of the LSI becomes extremely long. but.

According to the present invention, the output level can be measured with just two test patterns regardless of the number of LSI terminals and the complexity of the LSI functions, and it is clear that the LSI measurement time can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the functions of a conventional LSI, and FIG. 2 is a block diagram of an embodiment of the present invention. In the cause, 1
0...LSI Uni, ), 11...Input terminal, 12.21...Output buffer, 1B
, 14, 15°16.2B, 24.2 et al., 26...
...output terminal, 20...output buffer, control terminal, ? 6ru. Agent Patent Attorney Susumu Uchihara 1・' ・1, -j

Claims (1)

[Claims] A semiconductor device comprising a plurality of output buffers each having an output level uniquely determined by an external signal supplied from one external control terminal.