JPS6033309B2 - IC package wiring method - Google Patents
IC package wiring methodInfo
- Publication number
- JPS6033309B2 JPS6033309B2 JP9763779A JP9763779A JPS6033309B2 JP S6033309 B2 JPS6033309 B2 JP S6033309B2 JP 9763779 A JP9763779 A JP 9763779A JP 9763779 A JP9763779 A JP 9763779A JP S6033309 B2 JPS6033309 B2 JP S6033309B2
- Authority
- JP
- Japan
- Prior art keywords
- package
- terminals
- signal line
- terminal
- wiring method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は集積回路（ＩＣ）をパッケージに格納して使用
するＩＣパッケージに係り、特に、ＩＣの各信号線をパ
ッケージに設けられた端子に接続する際の信号線の配線
方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an IC package in which an integrated circuit (IC) is stored and used, and in particular, it relates to an IC package in which an integrated circuit (IC) is housed in a package. This article relates to a wiring method for signal lines when making connections.
一般のＩＣパッケージは、昭和３４年４月１５日に発行
された「最菊市Ｃ技術入力〔電子展望別冊〕」誠文堂新
光社版に記載されているように、一例として第２図及び
第３図に示すような構成となっている。General IC packages are shown in Figure 2 and The configuration is as shown in FIG.
ＩＣ（集積回路）２２はパッケージ２０内に収容され、
パッケージ２川こ設けられた端子２１にＩＣ２２より信
号線２３により接続して構成されている。An IC (integrated circuit) 22 is housed in a package 20,
An IC 22 is connected to a terminal 21 provided on two sides of the package by a signal line 23.
このようなパッケージにおいては、アナログ１Ｃのよう
にアナログ量を使用するＩＣにおいては、ＩＣパッケー
ジ２０の端子２１間に容量が生じ、特に高周波で使用す
る場合には、この容量のためにＩＣが正常に動作しなく
なる欠点があった。〔問題点を解決するための手段〕
本発明は、隣接して設けられた端子に対し交流的に同電
位の信号線を接続するようにしたものである。In such a package, in an IC that uses analog quantities such as analog 1C, a capacitance occurs between the terminals 21 of the IC package 20, and this capacitance prevents the IC from functioning properly, especially when used at high frequencies. There was a drawback that it stopped working. [Means for Solving the Problems] According to the present invention, signal lines having the same potential are connected to adjacent terminals in an alternating current manner.
第１図は本発明に搭載されるＩＣの一実施例である。 FIG. 1 shows an embodiment of an IC installed in the present invention.
図において、１，２，３，４はトランジスタ、５，６は
抵抗、７，８，９，１０，１１，１２は信号線端子をそ
れぞれ示す。In the figure, 1, 2, 3, and 4 are transistors, 5, 6 are resistors, and 7, 8, 9, 10, 11, and 12 are signal line terminals, respectively.
図のようにＩＣとして図のようにトランジスター，２に
より構成された差動増幅回路，負荷抵抗５，．６及び電
流増幅用トランジスタ３，４信号入力線端子として１１
，１２と出力線端子として７，８，９，１０より構成さ
れたアナログＩＣがあるとすると、各信号線端子より信
号線をＩＣパッケージに設けられた端子に接続する際に
、以下のように接続すればよい。As shown in the figure, the IC is a differential amplifier circuit composed of transistors 2, load resistors 5, . 6 and current amplification transistors 3 and 4 as signal input line terminals 11
, 12 and 7, 8, 9, and 10 as output line terminals. When connecting the signal line from each signal line terminal to the terminal provided on the IC package, do the following: All you have to do is connect.
信号線端子７，８及び９，１川ま交流的に同電位と考え
られるため、隣接するにパッケージ端子にはそれぞれ７
，８及び９，１０より引出された信号線を接続すればよ
い。すなわち、信号線端子８及び９の電位はトランジス
タ３及び４でそれぞれ構成された電流増幅器を介してェ
ミッタ端子より引き出された信号線端子と電位差は常に
一定である。Since the signal line terminals 7, 8 and 9, 1 are considered to have the same potential in terms of AC, the adjacent package terminals have 7, respectively.
, 8 and 9, 10 may be connected. That is, the potential difference between the potentials of the signal line terminals 8 and 9 and the signal line terminal drawn out from the emitter terminal via current amplifiers constituted by transistors 3 and 4, respectively, is always constant.
従って、この信号線端子７，８及び９，１０間の蓄積電
荷容量は常に一定で変化することがない。Therefore, the accumulated charge capacity between the signal line terminals 7, 8 and 9, 10 is always constant and does not change.
従って、交流的に容量がないのに等しい訳である。従っ
て、これら各信号線端子よりの信号線をＩＣパッケージ
の端子に接続すれば、この端子間の容量の影響は高周波
で動作させても皆無となる。又、入力端子１１，１２に
ついては同電位となるものがないため、等価的に交流的
に同電位の直流電位差のみを有する信号線を作成すれば
よい。Therefore, it is equivalent to having no capacity in terms of alternating current. Therefore, if the signal lines from these signal line terminals are connected to the terminals of the IC package, there will be no effect of the capacitance between these terminals even if the IC is operated at a high frequency. Furthermore, since there are no input terminals 11 and 12 at the same potential, it is sufficient to create a signal line having only a DC potential difference equivalent to the same potential as AC.
すなわち、例えば入力線に対して一種のアンプ回路を構
成せしめて、このアンプ回路の出力を入力線の接続され
たＩＣパッケージ端子の隣接端子に接続すればよい。又
、この場合は隣接する端子のインピーダンスを低くすれ
ば外乱の影響を受けなくなるため、特別に等価端子を設
ける場合はこのようにすればよい。That is, for example, a type of amplifier circuit may be constructed for the input line, and the output of this amplifier circuit may be connected to a terminal adjacent to the IC package terminal to which the input line is connected. Further, in this case, if the impedance of the adjacent terminal is lowered, the influence of disturbance will be eliminated, so if an equivalent terminal is specially provided, this may be done.
以上のようにＩＣの信号線をＩＣパッケージ端子に接続
する際に、ＩＣパッケージの隣接する端子に交流的に同
電位の信号線を接続すればよく、又に基本回路に交流的
に同電位のものがなければ等価的に同電位の信号線を作
成して接続するようにすれば、高周波でＩＣを動作ごせ
ても容量の影響を受けずに正常に動作するようになる。As described above, when connecting the IC signal line to the IC package terminal, it is sufficient to connect the signal line with the same AC potential to the adjacent terminal of the IC package, or connect the basic circuit with the same AC potential. If you don't have one, you can create and connect signal lines with equivalent potential, and even if you operate the IC at high frequencies, it will operate normally without being affected by the capacitance.
従って、本発明においてはＩＣパッケージの端子間容量
を皆無にでき、高周波でも正常に動作するにパッケージ
を提供出来る。Therefore, in the present invention, the capacitance between the terminals of the IC package can be completely eliminated, and a package can be provided that operates normally even at high frequencies.
第１図は本発明に係るＩＣの一実施例、第２図は本発明
に係るＩＣパッケージの外観図、第３図は本発明に係る
ＩＣパッケージの断面図を示す。
図において、１，２，３，４はトランジスタ、５，６は
抵抗、７，８，９，１０，１１，１２は信号線端子をそ
れぞれ示す。弟１図
第２図
第３図FIG. 1 shows an embodiment of an IC according to the invention, FIG. 2 shows an external view of an IC package according to the invention, and FIG. 3 shows a sectional view of an IC package according to the invention. In the figure, 1, 2, 3, and 4 are transistors, 5, 6 are resistors, and 7, 8, 9, 10, 11, and 12 are signal line terminals, respectively. Younger brother 1 figure 2 figure 3
Claims (1)
ケージに設けられた端子に接続するようにしたＩＣパツ
ケージであつて、少なくとも隣接して設けられた端子に
対し、交流的に同電位の信号線を接続するようにした事
を特徴とするＩＣパツケージの配線方法。1. An IC package in which an IC is housed in a package and each signal line of the IC is connected to a terminal provided on the package, in which a signal having the same AC potential as at least the adjacent terminals is connected. A wiring method for an IC package characterized by connecting wires.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9763779A JPS6033309B2 (en) | 1979-07-31 | 1979-07-31 | IC package wiring method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9763779A JPS6033309B2 (en) | 1979-07-31 | 1979-07-31 | IC package wiring method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5621356A JPS5621356A (en) | 1981-02-27 |
| JPS6033309B2 true JPS6033309B2 (en) | 1985-08-02 |
Family
ID=14197650
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9763779A Expired JPS6033309B2 (en) | 1979-07-31 | 1979-07-31 | IC package wiring method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6033309B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61153930U (en) * | 1985-03-15 | 1986-09-24 | ||
| JPH0443927Y2 (en) * | 1985-04-09 | 1992-10-16 |
-
1979
- 1979-07-31 JP JP9763779A patent/JPS6033309B2/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61153930U (en) * | 1985-03-15 | 1986-09-24 | ||
| JPH0443927Y2 (en) * | 1985-04-09 | 1992-10-16 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5621356A (en) | 1981-02-27 |
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