JPH0543478Y2 - - Google Patents
Info
- Publication number
- JPH0543478Y2 JPH0543478Y2 JP1987008401U JP840187U JPH0543478Y2 JP H0543478 Y2 JPH0543478 Y2 JP H0543478Y2 JP 1987008401 U JP1987008401 U JP 1987008401U JP 840187 U JP840187 U JP 840187U JP H0543478 Y2 JPH0543478 Y2 JP H0543478Y2
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- semiconductor device
- pellet
- pad
- lead terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000008188 pellet Substances 0.000 claims description 7
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 13
- 230000000694 effects Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
本考案は、半導体装置のボンデイングの取り方
に関し、特に高周波でのボンデイングワイヤの影
響を低減するための方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for bonding a semiconductor device, and particularly to a method for reducing the influence of bonding wires at high frequencies.
従来、この種の半導体装置としては第３図Ａに
示す様にペレツト３１上の１つの任意のパツド３
２より、外部端子３４へボンデイング・ワイヤ３
３を用いて、ボンデイングしている。この時、半
導体装置のボンデイング部の等価回路は例えば接
地端子（以下GND）を例に取れば同図Ｂに示す
様な等価回路になつていた。
Conventionally, as shown in FIG. 3A, this type of semiconductor device has one arbitrary pad 3 on a pellet 31.
2, bonding wire 3 to external terminal 34
3 is used for bonding. At this time, the equivalent circuit of the bonding part of the semiconductor device was as shown in FIG.
このように、等価回路上にボンデイングワイヤ
のインダクタンスが入つているため、高周波で動
作する半導体装置や高速動作する半導体装置では
この影響が大きく表われ、同図Ｃのように高い周
波数での利得特性の乱れ（ゲインのピーキングや
低下）や動作スピードの低下という欠点がある。
In this way, since the inductance of the bonding wire is included in the equivalent circuit, this effect is significant in semiconductor devices that operate at high frequencies or at high speeds, and the gain characteristics at high frequencies as shown in C in the same figure. It has the drawbacks of disturbances (peaking or reduction in gain) and a reduction in operating speed.
本考案の半導体装置は、前述のボンデイング・
ワイヤの影響をなくすためにペレツト上に任意の
容量値をもつた部分を形成し、この容量をボンデ
イング・ワイヤのインダクタンスを適当な周波数
で直列共振する様に設定し、ボンデイング・ワイ
ヤの影響をキヤンセルする様にしている。
The semiconductor device of the present invention uses the above-mentioned bonding and
In order to eliminate the influence of the wire, a part with an arbitrary capacitance value is formed on the pellet, and this capacitance is set so that the inductance of the bonding wire resonates in series at an appropriate frequency, thereby canceling the influence of the bonding wire. I try to do it.
次に本考案について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図Ａは本考案の一実施例を示す図である。
図でペレツト１１上で外部端子１７へ接続するペ
レツト上の配線１２はパツド１３→ボンデイング
ワイヤ１６→端子→１７への接続の他の並列にペ
レツト上の容量部分１４（例えばMOS容量）を
界してパツド１５→ワイヤ１８→端子１７への接
続がされて、かつ容量１４Ｃとワイヤ１８のイン
ダクタンスL2が直列共振する様に値が設定され
ている。したがつて、等価回路は同図Ｂのように
なる。 FIG. 1A is a diagram showing an embodiment of the present invention.
In the figure, the wiring 12 on the pellet that connects to the external terminal 17 on the pellet 11 separates the capacitive portion 14 (for example, MOS capacitor) on the pellet from the other parallel connection of the pad 13 → bonding wire 16 → terminal → 17. The connection is made from the pad 15 to the wire 18 to the terminal 17, and the values are set so that the capacitance 14C and the inductance L2 of the wire 18 resonate in series. Therefore, the equivalent circuit becomes as shown in FIG.
このような構成によれば、回路上の直流成分
は、ワイヤ１６を通し、交流成分は１６と１８の
両方を流れる様に実施されているため、同図Ｃの
ように任意の周波数でのピーキング現象等を直列
共振により交流インピーダンスを「零」にし、な
くす効果がある。 According to this configuration, the DC component on the circuit passes through the wire 16, and the AC component flows through both wires 16 and 18, so that peaking at any frequency can be avoided as shown in C in the same figure. It has the effect of reducing AC impedance to "zero" and eliminating phenomena, etc. by series resonance.
第２図は本考案の他の実施例を示す図である。
本実施例では同図の様に外部引出し端子を二つ１
７，１９に分け、それぞれへボンデイングを実施
しているため、等価回路は同図Ｂに示す様にな
り、容量部Ｃとインダクタンス（L2＋l2）を直列
共振する事により引き出し端子のインダクタンス
の影響までなくすという利点がある。 FIG. 2 is a diagram showing another embodiment of the present invention.
In this embodiment, two external lead terminals are used as shown in the figure.
Since the circuit is divided into 7 and 19 parts and bonded to each, the equivalent circuit becomes as shown in Figure B. By making the capacitor part C and the inductance (L 2 + l 2 ) resonate in series, the inductance of the extraction terminal can be reduced. This has the advantage of eliminating the effects.
本考案の実施例ではボンデイング・ワイヤのイ
ンダクタンスL1とL2や引出し端子のインダクタ
ンスl1とl2の値は完全には同じ値にならないが、
各々を極く近くに位置させておけば現在の組立て
技術ではほぼ同一の値に製造できる事は明らかで
ある。 In the embodiment of the present invention, the inductances L 1 and L 2 of the bonding wires and the inductances l 1 and l 2 of the lead terminals are not exactly the same value, but
It is clear that if they are located very close to each other, they can be manufactured to approximately the same value using current assembly technology.
また半導体装置の他の端子、例えば入出端子や
電源端子などへ本考案を実施しても同様の効果が
得られる事は明らかである。 It is clear that similar effects can be obtained even if the present invention is applied to other terminals of a semiconductor device, such as input/output terminals and power supply terminals.
以上のとおり、本考案によればボンデイングワ
イヤの影響を抑えた半導体装置が得られる。
As described above, according to the present invention, a semiconductor device can be obtained in which the influence of bonding wires is suppressed.
第１図は本考案の一実施例を示す図であり、Ａ
は構造図、Ｂ等価回路図、Ｃはゲインの周波数特
性を示す図である。第２図は本考案の他の実施例
を示す図であり、Ａは構造図、Ｂは等価回路図で
ある。第３図は従来例を示す図であり、Ａは構造
図、Ｂは等価回路図、Ｃはゲインの周波数特性を
示す図である。
FIG. 1 is a diagram showing an embodiment of the present invention, and A
1 is a structural diagram, B is an equivalent circuit diagram, and C is a diagram showing frequency characteristics of gain. FIG. 2 is a diagram showing another embodiment of the present invention, in which A is a structural diagram and B is an equivalent circuit diagram. FIG. 3 is a diagram showing a conventional example, in which A is a structural diagram, B is an equivalent circuit diagram, and C is a diagram showing frequency characteristics of gain.
Claims (1)
ボンデイング・パツドを有する半導体装置におい
て、前記ボンデイング・パツドと前記外部引き出
し端子との間を接続するボンデイングワイヤのイ
ンダクタンスと直列共振する容量値の容量部とこ
の容量部に接続された他の外部接続用パツドとを
さらに前記ペレツト上に形成し、前記外部接続用
パツドと前記ボンデイング・パツドとから並列に
前記外部引き出し端子へボンデイングし、前記直
列共振によりボンデイング・ワイヤの影響を低減
することを特徴とする半導体装置。 In a semiconductor device having a bonding pad on a pellet for connection to an external lead terminal, a capacitor part having a capacitance value that resonates in series with the inductance of a bonding wire connecting between the bonding pad and the external lead terminal; Another external connection pad connected to the capacitive part is further formed on the pellet, and the external connection pad and the bonding pad are bonded in parallel to the external lead terminal, and the series resonance causes bonding. A semiconductor device characterized by reducing the influence of wires.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987008401U JPH0543478Y2 (en) | 1987-01-22 | 1987-01-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987008401U JPH0543478Y2 (en) | 1987-01-22 | 1987-01-22 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63118234U JPS63118234U (en) | 1988-07-30 |
| JPH0543478Y2 true JPH0543478Y2 (en) | 1993-11-02 |
Family
ID=30792742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987008401U Expired - Lifetime JPH0543478Y2 (en) | 1987-01-22 | 1987-01-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0543478Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8791767B2 (en) * | 2010-10-29 | 2014-07-29 | Qualcomm Incorporated | Package inductance compensating tunable capacitor circuit |
-
1987
- 1987-01-22 JP JP1987008401U patent/JPH0543478Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63118234U (en) | 1988-07-30 |
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