JPS6033080A - Microcomputer for timepiece - Google Patents

Abstract

PURPOSE:To measure time intervals with resolution similar to a cycle time by switching and connecting the input to a counter dedicated to a chronograph to a high-frequency division output of a frequency dividing circuit according to a program. CONSTITUTION:A pulse generating circuit 5 inputs the frequency-division output of the frequency dividing circuit 3 which divides the reference frequency of an oscillation circuit 1 to generate a signal of specific frequency. Further, a signal selecting circuit 8 selects one of plural frequency-division outputs of relatively high frequency of the circuit 3 and impresses the output of the circuit 5 to the chronograph counter 20. Then, a control circuit 4 when detecting the execution of a specific instruction controls the circuit 8 and impresses the output of the circuit 5 or selected frequency-division output to the input of the counter 20.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a microcomputer for a watch, and in particular,
(b) Prior art regarding microcomputers for watches with built-in chronograph counters In recent years, semiconductor integrated circuits for electronic watches have come to be formed using dedicated microcomputers. In this Ritt microcomputer, various functions of the watch are realized by programs. Of course, the chronograph function is also realized by a program, but the processing speed of a watch microcomputer is not that fast. . Second-digit measurements cannot be achieved by programming. Therefore, /10
A microcomputer for watches has been developed that has a built-in counter dedicated to counting the 0-second digit.

On the other hand, in such a clock microcomputer,
If there is no chronograph function in the watch specifications, the dedicated counter with /10 seconds digits will not be used at all.

Recently, microcomputers for watches are increasingly being used to control electronic devices, taking advantage of their low voltage and low current consumption characteristics, and some of these application cages include microcomputers for watches. Sometimes it is necessary to measure time intervals with a resolution comparable to the cycle time of a computer. Generally, a timer counter that is installed inside the micro combinator and can be preset by a program is used.
Since the timer time is measured by detecting the carry signal, it is impossible to measure the time interval with the same resolution as the cycle time. Furthermore, in order to realize this function, it is necessary to separately provide a counter whose counting contents can be read out by a program, and in this case, the chip area of the micro combinator increases, which is undesirable.

(c) Purpose of the Invention The present invention has been made in view of the above-mentioned points, and uses a dedicated chronograph counter, and its input is switched and connected to a relatively high frequency divided output of a frequency dividing circuit by a program. By making it possible to do so, it is possible to provide a microcomputer for time 1 that is capable of measuring time intervals with a resolution equivalent to that of cycle time.

B) Structure of the Invention The present invention comprises a frequency dividing circuit that divides a reference frequency signal, a pulse generating circuit that receives the divided output of the frequency dividing circuit as input and generates a signal of a predetermined frequency, and the pulse generating circuit. In a watch microcomputer equipped with a chronograph counter that counts pulses, a plurality of relatively high frequency divided outputs of the frequency dividing circuit are applied, and any one of the plurality of frequency divided outputs is applied. a selection circuit that selects and outputs the pulse generation circuit; a switching circuit that switches between the output of the pulse generation circuit and the output of the selection circuit and applies it to the chronograph counter; and a control circuit that controls the circuit and the switching circuit and applies the output of the chronograph generating circuit or the selected divided output to the input of the chronograph counter, In addition to using it in clog 2f mode,
The configuration is such that it can be used as a counter that measures time intervals with the same resolution as cycle time.

(e) Examples FIG. 1 is a circuit diagram showing an embodiment of the present invention.

The oscillation circuit (1) consists of a crystal resonator (2) connected to an external terminal.
), e.g. 32,76811
y.

The reference frequency of oscillation is lost, and its oscillation output da. is the frequency divider circuit (
3) is applied. The frequency dividing circuit (3) is a T-FF (T-7
The reference frequency signal from the oscillation circuit (1) is constructed by continuously connecting 15 stages of lip-flops. Separate and lH
Outputs the z clock signal. Furthermore, among the divided outputs of each stage of the frequency dividing circuit (3), the divided output 1+ of the first stage is applied to the clock generator (4), while the divided output 0
7～〆3. is applied to the pulse generating circuit (5).
+■"-ノ = -1 to -ノ -7) e, -11
Timing signals T1, Tt, T5, and T4 for controlling the tongue 11v are generated and supplied to each internal circuit. Using the frequency division output OI (・timing signal T+
, Tt, T5, and T4, the cycle time of the microcomputer is 7168 seconds to perform 244-digit counting) (Create and output a pulse.This/second)
The pulse is input to an AND gate (7) controlled by the output Q of T-, FF (6).

T-FF (6) is a switch signal SW generated when a predetermined switch is operated in chronograph mode.
, and in the AND gate (7) ~), 1/
00 controls the conduction and interruption of the second pulse, and controls the start and stop of the chronograph.

Furthermore, the division output door 8, U, D, and oscillation output G of the frequency dividing circuit (3). is applied to the selection circuit (8). The selection circuit (8) is an AND game) (9) Oll) (OR with 13)
game) (consists of 13, AND game) (9) QIQυ
(An oscillation camera is connected to one input of 13.
, Da, are applied, and a control signal instructing selection of Tame, Tame, and G3.03 is applied from the control circuit α4) to the other input. That is, the control signal selects the oscillation outputs 0, 0, 8, and 9 by controlling the conduction and cutoff of AND gates (9), (11), and (12). The output is output via an OR gate Q3).

The output of the AND gate (7) is formed from the switching circuit 05B, AND gate) Qf9 (17) and the R gate, and one input of the AND gate (16) is applied with a /10 second pulse. is applied, and the output of the selection circuit (8) is applied to one input of the AND gate 07.

Furthermore, the control circuit M is connected to the other input of ANDG)QGI.
Q4) No R-8F FQ'l no output Q force application, SN
The output Q of R-8FF (11) is applied to the other input of D game) Q7). That is, the switching circuit α9 is the control circuit Q4) 17) R-8FF (IIK Yotsu"C control 11tt
, R-8FF (11 or in the reset state, the AND gate (the force output is
It is applied to the chronograph counter (21) via the O gate and the OR gate 081, and when R-5FFa9 is set, the output of the selection circuit (8) is applied to the chronograph counter (A). In other words, in the former case is a chronograph mode, and the latter is a mode that measures time intervals at arbitrary frequencies.

The chronograph counter (A) is a 10-base 13CD counter, which counts the pulses applied from the switching circuit 09, multiplies 10 pulses by nI, and sets R-8FF (2υ) by the output carry. .

R-8FF (21) is a 7-lip flop that stores the occurrence of an interrupt request, and the output Q of R-8FF (21) is output as an interrupt request signal IN'I'REQ. This interrupt request signal INTREQ is applied to an interrupt control circuit (not shown) inside the microcomputer, and when the interrupt is accepted, the interrupt request signal INTREQ is applied to an interrupt control circuit (not shown) inside the microcomputer. I got it. Addition processing and the like are performed on the count data of second digits and above, and in a mode in which time intervals are measured at an arbitrary frequency, addition processing and the like are performed on the count data of the upper digits provided in the RAM. On the other hand, when one interrupt is accepted, the interrupt set signal I is output from the interrupt control circuit.
NTHESET is 01 (R-8F via gate (2 Enoki)
Applied to the 'J set) terminal H of F (21), R-8FF
(2υ is reset. Also, the 4-bit output of the chronograph counter 01 is connected to the 4-bit data bus 35) via the transmission !/gate (24) controlled by the NOROR gate 081 output. Ru. NOR gate (23) and NAND gate 06) are 16
The instruction code sent to the bit instruction signals IRO to 1R15 is the chronograph counter (flood 4
MCD instruction (MoveCll) for reading numerical data
rono Counter Data to AC&n
, x), and when the MCD instruction is executed, the transmission gate (24
) is conductive, and the chronograph counter (i of 2I
iI number data is sent to the data bus (c).

A control circuit (
14) applies the output of the selection circuit (8) to the input of the chronograph counter (A) and outputs the oscillation output. , s to add one of the divided outputs G8, D2, G.
cT command (Set (!chrono Counter
The NOR gate (2η and N A N ]) which detects that the instruction code indicating TimerMode ) is sent to the instruction signals I n O to I R15 (2 η and N A N ]) gate (2
ILCT command (Re5et Chrono
The instruction code indicating "Counter Timer Mode" is the instruction signal IitO~l1ll.
N OIt gate c2 detects that it has been sent to
R-8FF (1!J, which controls the switching of the switching circuit Q51 and the NAND gate output), and the divided outputs G0 and D7.08. A latch circuit C311 (32
1 (composed of 3 moats (34). R-8FF (1! The NOROR gate 081 force is applied to the set terminal S of 11, and the initial setting signal - @MR and N0rt gate is applied to the reset terminal R) (2! The output of e is applied via the OR gate (4. Also, the latch circuit cll) (321(, +:<
Instruction signals IRO1IRI, IIt2, and In2 are applied to the input terminals of 104), respectively, and the output Q is applied to the corresponding ANI) gate (9) 4α11Q2
1. Furthermore, the latch circuit C3])C32C3
3) The clock terminal of 434) has a NOR gate 07.
) is applied in common, and the reset terminal R is NOR
The outputs of the gates ψ are commonly applied. Therefore, S
The CT instruction is executed and the output of NOR gate 07) becomes 1"
Then, R-8FFB! J is set, and the data sent to the instruction signals IRO to IR3 is captured and stored in the latch circuit C3+1 (321C3□□□C34). On the other hand, when the RCT instruction is executed and the output of the NOR gate becomes R1'', R-8FF (
191 is reset, and the latch circuit <31)4
321G3■04) are all reset.

Figure 2 shows the above-mentioned SCT instruction, RCT instruction and MCD
FIG. 3 is a diagram showing an instruction code of an instruction. The SCT command uses IRI1. out of the 16-bit instruction signals. I
RI 3, lR14, Ill 5 are R1'', In
8. IRQ, IRIO1 is a code where R12 is θ'', and it is set to IRQ-In3, so X3 gives the selection circuit (8) an oscillation output of 0°, a frequency division output of 2,
You can instruct the selection of That is, when Xo is set to R1'', an oscillation output of 0° (16,384Hz) is specified, and X.

When set to 1'', the divided output OI (8pl 92H7
) is specified, and if Xi MIG 1 is specified, the divided output 'A
(4,096117,) is specified and when X3 is set to "1", the frequency division output Is (2t O4811Z) is specified. In order to detect this SCT instruction, the NOR gate (27) and the NAND gate (27) shown in FIG.
In c), instruction signals IR8 and IR9
, IRIO1, IR12 are applied to the N0It gate C, 1, R11, 1R13, 1R14, 1R15 and the timing signal T3 are applied to the NAND gate (2B). Therefore, for example, when an SCT instruction with Xo set to R1'' is executed, at the timing of the timing signal T3, the output of the NOR gate (the output of the two swords becomes R1'', so R
-8FFQ! J is set, and R is set in the latch circuit C31).
1", "O" is stored in the latch circuit (32 (33) C34). Therefore, the oscillation output G is output from the selection circuit (8) via the ANDNO gate and OR gate (13Y), and The switching circuit a9 applies the applied oscillation output D to the chronograph counter C!α.Thereby, the chronograph counter (201 is the oscillation output D) is divided.

In addition, in FIG. 2, the RCT instructions are instruction ID number I R10, IRI 1, II't13, I
R14, 1ll15 is R1'', In8, In9
, lR12 is a code based on pa0'' and 1, and IRO~I
IL7 is undefined. To detect this RCT command, the NOR gate 0! shown in FIG. j and NAND
C3fl), the instruction signals IR8, IR9, lR12 and the output of the NAND gate 00) are applied to the NOR gate (29), and the instruction signal ■RIO1IR is applied to the NAND gate 00).
11, lR13, lR14, lR15 and timing signal T3 are applied. Therefore, when this RCT command is executed, at the timing of the timing signal T3, N
The output power of the OR gate becomes ``1'', and this pulse causes the output of ``UR-8F F'' (19 and latch circuit C3])
C32)C33)(1341) is reset. Therefore, the output Q of the latch circuit C31)C12CklC34)
The oscillation output 96o and the frequency division output DA3.96!, DA, are all '0'', and the AND gate (8) of the selection circuit (8)
On the other hand, the switching circuit (19 is an AND gate) (to apply the force output to the chronograph counter (2), the start and stop are controlled by switch operation. The chronograph mode is set in which the chronograph counter (2υ) counts /10 second pulses.

Furthermore, in FIG.
R13, I]114 is '1'', In8, In9,
IRII, TR15 is a code that becomes '°0',
Lower 7 bits X. -X6 is used as data specifying the address of the RAM where the read data is to be stored. In order to detect this MCD instruction, the NOR game shown in Figure 1) ('2' (+ and NAND game)
(In 261, instruction signals IR8, I
li9, I R11, In15 are applied to NOR gate 03), In7, I R10, IR12, IR13,
lR14 is applied to the NAND gate (26). This MCD command is executed when reading out the counted contents of the chronograph counter (2i) in the chronograph mode or the time interval measurement mode at the selected frequency, and the MCD command is executed. Then, the output of the NOR gate (23) becomes 1", the transmission gate (C!4) becomes conductive, and the chronograph counter (23) becomes conductive.
20) is sent to the data bus (251),
The data is stored in RAM specified by the lower seven pits of the MCD instruction.

In the embodiment shown in FIG. 1, R-8FF (1
! Since the '11 (20 and T-FF (6)) are reset, the input of the chronograph counter (201) is connected to the output of the AND gate 1 (7), or the '100 second pulse is
It is in a state where it is blocked by the D gate (7).

Furthermore, in the embodiment shown in FIG. 1, the latch circuit (31
Instruction signals IRQ, IRI, IR2, and IR3 are applied to the input terminals of the 1t321G31C341. If a method of specifying is adopted, the input terminals LK & M of the latch circuit 431) (321-04) are connected to the data bus (two bits each). After sending the data specifying the , by executing the SCT command,
Data specifying the frequency is stored in the latch circuit C'1l) (32 (g) (34)).

In this way, multiple signals with frequencies equal to or close to the cycle time are taken out from the frequency dividing circuit (3), etc., and the frequencies are specified by the SCT command, and the specified frequencies are By counting with a chronograph counter (20), it is possible to measure time intervals with various resolutions that are equal to or close to the cycle time.

(F) Effects of the Invention As described above, according to the present invention, it is possible to fully satisfy the functions required when a watch microcomputer is used to control various electronic devices, etc. It has the effect of expanding the scope of application.

[Brief explanation of the drawing]

FIG. 1 is a logic circuit diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing instruction codes used in the embodiment of FIG. Explanation of main drawing numbers (11...Oscillation circuit, (2)...Crystal resonator,
(3)...Frequency divider circuit, (4)...Clock generator, (5)''/100 second pulse generation circuit,
(8)...Selection circuit, 04)...Control circuit, α
9...Switching circuit, (20)...Chronograph counter, (251...Data bus.

Claims (1)

[Claims] 1. A frequency dividing circuit that divides a reference frequency signal, a pulse generating circuit that receives the divided output of the frequency dividing circuit as an input and generates a signal of a predetermined frequency, and a pulse generator of the pulse generating circuit. In a watch microcomputer equipped with a chronograph counter for counting, one of the plurality of relatively high frequency divided outputs of the frequency dividing circuit and the output of the pulse generating circuit is selected. A signal selection circuit applies the signal to the chronograph counter, and when it detects that a predetermined command has been executed, controls the signal selection circuit and applies the output of the pulse generation circuit or the selected signal to the input of the chronograph counter. and a control circuit for applying a frequency-divided output. 82. In claim 1, the signal selection circuit includes a selection circuit that selects a plurality of relatively high frequency divided outputs of a frequency division circuit, and an output of the selection circuit and the pulse generation circuit. A microcomputer for a watch, comprising a switching circuit that switches the output of the circuit.