US3817020A

US3817020A - Electronic digital clock

Info

Publication number: US3817020A
Application number: US00249792A
Authority: US
Inventors: M Esaki
Original assignee: NipponDenso Co Ltd
Current assignee: Denso Corp
Priority date: 1971-05-04
Filing date: 1972-05-03
Publication date: 1974-06-18
Anticipated expiration: 1991-06-18

Abstract

A pulse signal having a constant period shorter than that of a quick feed signal and signals transmitted through the actuation of a quick feed switch are used to trigger flipflops and the flipflops deliver signals corresponding to the time of actuation of the switch. The quick feeding operation is performed by applying the quick feed signal to counter circuits only while the signals corresponding to the time of switch actuation are being delivered. In this way, an erroneous operation due to the chattering of the switch can be completely eliminated so that the desired quick feed operation can be accurately performed and that the reference clock signal together with the quick feed signal can be applied to the counter circuits.

Description

United States Patent [191 Esaki ELECTRONIC DIGITAL CLOCK [75] Inventor: Motoharu Esaki, Oobu, Japan [73] Assignee: Nippondenso Co., Ltd, Kariya-shi, Aichi-ken, Japan [22] Filed: May 3, 1972 [21] Appl. No.: 249,792

[30] Foreign Application Priority Data [111 3,817,020 1 June 18, 1974 Primary Examiner-Richard B. Wilkinson Assistant ExaminerU. Weldon A pulse signal having a constant period shorter than that of a quick feed signal and signals transmitted through the actuation of a quick feed switch are used to trigger flipflops and the flipflops deliver signals corresponding to the time of actuation of the switch. The quick feeding operation is performed by applying the quick feed signal to counter circuits only while the signals corresponding to the time of switch actuation are being delivered. In this way, an erroneous operation due to the chattering of the switch can be completely eliminated so that the desired quick feed operation can be accurately performed and that the reference clock signal together with the quick feed signal can be applied to the counter circuits.

2 Claims, 9 DrawingFigures PfP/Of? 14/? T May 4, 1971 Japan 46-29686 [52] US. Cl. 58/23 R, 513/855 [51] Int. Cl. G04b 27/00 [58] Field of Search... 58/23 R, 23 A, 23 AC, 23 D, 58/33, 34, 57, 85.5

[56] References Cited UNITED STATES PATENTS 3,195,011 7/1965 Polin 58/23 AC 3,258,906 7/1966 Demby 58/23 X 3,485,033 12/1969 Langley 58/23 R 3,664,116 5/1972 Emerson et a1.. 58/23 A 3,672,155 6/1972 Bergey et a1 58/85.5 X

COUNTER COUNTER COUNTER Owe/r FEED a CIRCUIT BQMQ P'ATENIEDm 18 an sum 3 0? 4 COUNTER COU/VTER COUNTER FIG. 5

' T/ME 1 ELECTRONIC DIGITAL CLOCK BACKGROUND OF THE INVENTION clock in which the desired time quick feeding operation is performed through a quick count faster than the normal one due to the application of a quick feed signal having a period shorter than that of a reference Clock signal to counter circuits.

.. .2.- PFS P DUB? BliQ 1 The conventional electronic digital clock which is similar in principle to that according to the present invention is as illustrated in FIG. 1 of the attached drawings. In a quick feed circuit 2900, a minute clock signal having a period of one minute and received at a tenninal a is fed through the normally closed contact 2901 a of a single-pole double-throw switch 2901 to a decade minute counter circuit 1700. Then, the output of the counter 1700, which is delivered every 6 minute-clock pulses, is applied to a divide-by-six counter circuit 1800, which in turn delivers at a terminal b an hour clock pulse signal having a period of 1 hour. Namely, the output of the divide-by-six counter 1800 is-delivered every 60 minute-clock pulses reaching the terminala. The hour clock signal is fed through'the normally closed contact 2902 a of a single-pole doublethrow switch 2902 to an hour counter circuit 1900. Now, if the minute quick feeding operation is desired, the switch 2901 has only to be changed over. Namely, if the movable contact of the switch 2901 is shifted from the normally closed contact 2901 a to the normally open contact 2901 b, aquick feed pulse signal having a period of 0.5 second and applied to a terminal c, is fed to the decade minute counter 1700 to perform the minute quick feeding operation. When it is desired to stop the quick feeding operation, it is only necessary to make the switch 2901 resume its initial state that the movable contact is in engagement with the stationary contact 2901 a. On the other hand, if the hour quick feeding operation is desired, the switch 2902 has only to be actuated. The quick feed signals used in both the cases, i.e..minute and hour quick feed operations, are the same and derived at the terminal 0.

However, the conventional electronic digital clock as described above'is largely influenced by the chattering of the

switch

2901 or 2902. This is explained below by reference to FIG. 2 of the attached drawings. FIG. 2(-A) shows the minute clock pulse signal applied to the terminal a, FIG. 2(B) illustrates the quick feed pulse signal applied to the terminal c, FIG. 2( C) depicts the ideal quick feed pulse signal which is considered to be applied to the input terminal of the decade minute v counter 1700 in case where the switch 2901 causes no chattering, and FIG. 2 (D) represents the actual quick feed pulse signal which contains chattering components and is applied to the input terminal of the decade minute counter 1700. In these figures, the time base is measured on the same scale. Under ideal conditions, the quick feeding operation starts at time T and ceases I at'time'T Actually, however, chattering generated between time T and time T and between time T and time T ,'as seen in FIG. 2( D), will cause an operational possible to quickly shift the counter 1700 exactly for any desired period of time since the duration of chattering is rather indefinite. For this reason,

capacitors

2903, 2904, 2905, 2906 and 2907 are connected between the contacts of the

switches

2901 and 2902 and the ground so as to absorb and eliminate the noises due to chattering, as seen in FIG. 1. However, it is impossible to completely eliminate the chattering noises with such capacitors, and there is still a small probability that an erroneous operation will occur. Moreover, with the conventional electronic digital clock as shown in FIG 1, it is necessary for the minute clock pulse signal or the hour clock pulse signal to be cut off when the quick shift pulse signal is applied to the minute counter 1700 or the hour counter 1900, respectively. Consequently, two separate single-pole double-

throw switches

2901 and 2902 have to be used respectively for the minute counter 1700 and the hour counter 1900. And this adds to the complexity constitution.

SUMMARY OF THE INVENTION Accordingly, the object of the present invention is to provide an electronic digital clock wherein a pulse signal having a constant period shorter than that of a quick feed signal and signals transmitted through the actuation of a quick feed switch are used as signals for triggering flipflops, which deliver signals corresponding to the time of actuation of the switch, wherein the quick feeding operation is performed by applying the quick feed signal to counter circuit only while the signals delivered from the flipflops are lasting so that the desired quick feeding operation can be performed very accurately without suffering from erroneous operation due to the chattering of the quick feed switch, and wherein the reference clock signal is not interrupted but superposed on the quick feed signal so that the superposed signals can be applied to the counter circuits.

Therefore, an electronic digital clock according to the present invention comprises flipflops which receive as their trigger signals the pulse signal having a constant period shorter than that of the quick feed signal and the signals transmitted through the actuation of the quick feed switch and which deliver as their outputs the signals corresponding to the time of actuation of the switch, and gate circuits which during quick feeding operation feed the quick feed signal to the counter circuits only while the flipflops are delivering their outputs, so that even if noise is generated due to the chattering of the quick feed switch, the actuation of the quick feed switch is accurately detected due to the memory effect of the flipflops. Consequently, erronedisturbance. Namely, spurious pulses due to chattering between T, and T and between T andT, make it imeliminated and the desired quick feeding operation can be very accurately performed.

The above mentioned gate circuits comprise gates which take the logical product of the outputs of the flipflops and the quick feed signal and gates which take the exclusive OR logic sum of the outputs of the gates and the reference clock signal. Accordingly, the reference clock signal need not be interrupted when the quick feed signal is applied to the counter circuits, as is not the case with the conventional electronic digital clock in which the reference clock signal must be interrupted whenever the quick feed signal needs to be applied to the counter circuits. On the contrary, the quick feed signal can be superposed on the reference clock signal and the superposed signals can be applied to the counter circuits. Therefore, such a special circuit for interrupting the reference clock signal, as is usually in-- corporated in the conventional electronic digital clock,

is not needed. This simplifies the manipulation and the constitution of the device.

BRIEF DESCRIPTION OF THE DRAWINGS F IG. 6 shows the waveforms of signals necessary for explaining the operation of a monostable time-limit circuit used in the electronic digital clock according to the invention.

. FIG. 7 shows the waveforms of a quick feed signal, the output signal from the flipflop and the resulting signal detained through the combined effect of the two previous signals.

FIGS. 8 and 9 show the waveforms of signals necessary for explaining the inputs to and the outputs from exclusive OR gates used in the electronic digital clock according tothe invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT Now, the preferred embodiment of the present invention will be described with reference to FIG. 3. In FIG.

3, a signal having a frequency of 2" Hz, delivered from. a stabilized oscillator 1100, is applied to a frequency divider 1200' having a dividing factor 2 T so that a signal having a period of 0.125 second (hereinafter referred to as a 0.125 sec signal") appears at a terminal d. The 0.125 sec signal is also fed to

frequency dividers

1300 and 1400, each having a dividing factor 2, so. as .to be further frequency-divided so that a quick feed signal having a period of 0.5 second is developed at at terminal e. The quick feed signal is further frequencydivided through a frequency divider 1500 having a dividing factor 2" to develop a signal having a frequency of I H: (hereinafter referred to as a 1 sec signal) at a terminal f. The l sec signal is then applied to a fre-' quency divider circuit 1600 designed for a dividing factor 60" to be converted to a minute clock signal having a period of 1 minute, which is fed to a time feeder circuit 2200. The minute clock signal from the minute output of the time feeder circuit 2200 is sent to a decade minute counter circuit 1700, the output of which is connected with a divide-by-six minute counter 1800. The divide-by-six minute counter 1800 delivers a signal having a period of one hour, i.e. hour clock signal,

which is fed through the time feeder circuit 2200 to a til divide-by-l2 counter circuit consisting of a decade 6 hour counter 2000 and a clear circuit 2100. The outputs of the decade minute counter 1700, the divide-by- 6 minute counter 1800, the decade hour counter 1900 and thedivide-by-2 hour counter 2000 as BCD codes are applied respectively to solid-state

numeric indicator

2400, 2500, 2600 and 2700 to give digital representation of time. Each of the

digital display devices

2400, 2500, 2600 and 2700 comprises a BCD-to-decimal deqodqtand..lisbtsmittin dei.

Referring now to FIG. 4, there is illustrated the above mentioned time feeder circuit 2200 which comprises a monostable time-limit circuit constituted of

inverters

2201, 2202 and 2203 and a NAND gate 2204; two R-S flipflops constituted of

NAND gates

2205, 2206 and 2207, 2208;

NAND gates

2209 and 2210 constituting digital switches; and exclusive OR

gates

2211 and 2212. The hour quick feeder circuit comprising the

NAND gates

2205, 2206 and 2209 and the exclusive OR gate 2211 has the same circuit configuration and operates in V the same manner as the minute quick feeder circuit comprising the

NAND gates

2207, 2208 and 2210 and the exclusive OR gate 2212, and therefore only the operation of the minute quick feeder circuit will be described below asan example of time quick feeding operation.

FIG. 5A shows the 0.125 sec signal applied to the terminal d in FIG. 4, and FIG. 5(B) shows a signal appearing at a terminal g in F IG. 4 which signal is converted from the 0.125 sec signal through the monostable timelimit circuit comprising the

inverters

2201, 2202 and 2203 and the NAND gate 2204 and hereinafter referretq.aliensisnalif a... a. l. First, the operation of the monostable timelimit circuit will be described by the help of the waveforms When the 0.125 sec signal shown in FIG. 6(A) skips from its 0 level to its I level at time To, the output of inverter 2201 is reversed after a delay time T T which time delay is characteristic of a the inverter and delivers an output signal as shown in FIG. 6(8). The reversal of the input signal to inverter 2201 in turn forces the inverter 2202 to be reversed after a delay time T T so that the latter delivers an output signal as shown in FIG. 6(C). The output signal is then reversed, while being delayed by a time T T through the inverter 2203, which delivers an output signal as shown in FIG. 6( D) having a delay vT T with respect to the 0.125 sec signal. The NAND gate 2204 takes the NAND of the signals in FIGS. 6(A) and 6(D) and produces a set signal as shown in FIG. 6( E). Theset signalhas a duration T, T equal to the sum of the delay ms tqiths. this?.inv rtsnfilllli22 M220 FIG. 5( C) shows the waveform of a voltage available when a manual switch 2300 is actuated, in which the time T to T is the period during which the movable contact of the manual switch 2300 is engaged with the contact 2300 a to perform the minute quick feeding operation and in which irregular pulses appearing for t, and t correspond to chattering noises. FIG. 5(D) :I"he truth table for the R-S flipflop is given below.

5' 6 TRUTH TABLE 1 TRUTH TABLE 11 input terminal output terminal input terminal output terminal 2212a 2212 h 2212 r R S Qt,,+l n l 0 0 0 u l l 0 1 l 1 I 0 0 l 0 I 1 Q1" 1 I o Th operation f h R fli fl i now b As stated in the description concerning the wavescribed. It should here be noted that the signals shown in FIGS. 5(C) and 5(8) are applied to the terminals R and S, respectively. Reference should now be made to FIGS. 5(A) to 5(D). Before the time T the signals at the terminals R and S have both the level 1 so that the output Q ismaintained at the level before the time T as seen in the above truth table. Upon the arrival of the time T the input signal to the terminal S turns to 0 level and then holds the 0 level for a very short time. During this period, the input signal to the terminal R is at its 1 level while the input signal to the terminal 5 falls to its 0 level, so that the output Q assumes the level 0, as seen in the truth table given above. Next, when the time T is reached, the input to the terminal R falls to the 0 level while the input to the terminal S is at the I level, so that the output Q, as seen in the truth table,

has the 1 level. At the time T noise due to chattering of the switch 2300 starts and lasts for a period t,. How-- ever, the flipflop does not change its state whether the level of the input to the terminal R is O or 1, since the level of the output at the terminal Q of the R-S flipflop is maintained at l.

The minute quick feeding operation terminates at time T and the input to the terminal R is shifted from its 0 level to its 1 level. At the same time, noise due to chattering of the switch starts again and last for a period r Also in this case, however, the flipflop is not actuated for the same reason as stated above. And at T,,, as soon as the level of the input to the terminal S has been changed from I to 0, the level of the output Q be comes 0. Thus, owing to such an operation of the R-S flipflop as described above, noise due to the chattering of the switch can be completely eliminated, that is, a

wave shaping effect can be enjoyed.

FIG. 7(A) shows a quick feed signal applied to a terminal e in FIG. 4. This quick feed signal is controlled by the output of the R-S flipflop shown in FIG. 7(B) (corresponding to the waveform as shown in FIG. 5( D)) and fed to the input of the NAND gate 2210 only when the output of the RS flipflop is at the 1 level which is attained only when the manual switch, i.e. time quick feed switch, 2300 is actuated. This is manifested in FIG. 7(C). If the manual switch 2300 is not actuated, the level of the output from the R-S flipflop is 0 so that the level of the output of the NAND gate 2210 will be I, as seen in FIG. 8( A). The truth table II for the exclusive OR gate 2212 is given below. The operation of the gate 2212 will be understood by reference to the table II. Namely, a minute clock signal as shown in FIG. 8(8), applied to a terminal j in FIG. 4 is passed through the gate 2212 to be converted to the reversal of the minute clock signal, as seen in FIG.,8(C). The inverted minute clock signal is fed to the decade minute counter 1700 and the ordinary minute counting operation is performed.

forms in FIG. 7, if the movable contact of the switch 2300 is engaged with the contact 2300 a, the level of the input to one of the input terminals of the NAND gate is changed from O to 1, as seen in FIG. 7(B), so that the quick feed signal as shown in FIG. 7(A) is converted to one, as shown in FIG. 7(C), that is fed to the input terminal 2212 a of the exclusive OR gate 2212. The exclusive OR gate 2212, with an input as shown in FIG. 9(A) (which corresponds to the waveform shown in FIG. 7(C)) applied thereto, delivers an output signal whose waveform is as shown in FIG. 9(C) to the scaleof-lO minute counter 1700, when the level of the minute clock signal, as shown in FIG. 9(8), applied to the input terminal 2212 b is 1. If the level of the minute clock signal is 0, as seen in FIG. 9(D), the waveform of the output of the exclusive OR gate 2212 is as shown in FIG. 9(E). The quick feed signals appearing a period T T as shown in FIGS. 9(C) and 9(D) triggers the scale-of-lO minute counter 1700 so that the quick feed operation will be performed. In this case, when the quick feed signal is applied to the decade minute counter 1700, the quick feed signal can be superposed on the normal clock pulse signal. Namely, the normal minute clock pulse signal need not be interrupted in case of the application of the quick feed signal to the counter 1700.

The foregoing description is for the minute quick feeding operation, but a similar description will be true. Namely, if the contact 2300 b is closed, the quick feed signal appears at the output terminal of the exclusive OR gate 2211, as in case of the minute quick feeding operation, and the hour quick feed signal is applied to the decade hour counter 1900 so that the hour quick feed operation will be performed.

It should here be noted that the present invention is not limited to the above described embodiment but that various modifications are to be devised, such as one in which a tuning fork or a monostable multivibrator is used to generate stabilized oscillations in the oscillator circuit 1100, and one in which the

digital display

2400, 2500, 2600 and 2700 are some kinds of glow tubes.

What we claim is:

1. An electronic digital clock comprising a clock signal generator, a plurality of frequency dividers for dividing the output of said clock signal generator, said frequency dividers providing a quick feed signal at a quick feed output and a control signal at a control output thereof, time display means, and time feeding .means for coupling another output of said frequency dividers to said time display means, said time feeding means including time setting means comprising a manual switching means for initiating time feeding, a set signal generator connected to said control output, a akefiflk lqtfiw haying Output terminal nd 2. An electronic digital clock according to claim 1 wherein said time feeding means further includes an exclusive OR circuit connected between said NAND circuit and said time display means for taking the exclusive logical sum of the output of said NAND circuit and the divided clock signal from the output of said feik iztqi iqstst, it

Claims

1. An electronic digital clock comprising a clock signal generator, a plurality of frequency dividers for dividing the output of said clock signal generator, said frequency dividers providing a quick feed signal at a quick feed output and a control signal at a control output thereof, time display means, and time feeding means for coupling another output of said frequency dividers to said time display means, said time feeding means including time setting means comprising a manual switching means for initiating time feeding, a set signal generator connected to said control output, a set-reset flip-flop circuit having an output terminal and a pair of input terminals, one of which is connected to said manual switching means and the other of which is connected to said set signal generator, a NAND circuit having two input terminals, one of which is connected to said output terminal of said set-reset flip-flop circuit and the other of which is connected to said frequency divider for receiving said quick feed signal, said NAND circuit further including an output terminal operatively connected to said time display means.

2. An electronic digital clock according to claim 1 wherein said time feeding means further includes an exclusive OR circuit connected between said NAND circuit and said time display means for taking the exclusive logical sum of the output of said NAND circuit and the divided clock signal from the output of said fequency dividers.