JPS6030958B2 - electronic musical instruments - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION In electronic musical instruments, priority selection storage circuits are sometimes required for various applications.

The present invention provides an electronic musical instrument equipped with a priority selection storage circuit that is simple in configuration, easy to integrate into an integrated circuit, and easily expandable in scale by using a storage circuit with a special function. This was done with the aim of making it possible to easily obtain an electronic musical instrument with excellent performance. 1 and 2 are block diagrams illustrating different embodiments of conventional priority selection storage circuits in electronic musical instruments, respectively. The example shown in FIG. 1 includes switches Kit, K2t, . . . A so-called transfer switch is used to configure a priority circuit by the mechanical structure of the switch, and the setting operation for flip-flops FF1, FF2, etc. used as a memory circuit is performed by setting the switches corresponding to each flip-flop. This is performed when the make contact m is turned on and a set input is applied to the set terminal S. Furthermore, the reset operation for each flip-flop FFI, FF2, etc. is performed by each flip-flop FF1, FF2, etc. The inversion operation of the voltage at the Q terminal is taken out by differentiating circuits D1, D2... and sent to each flip-flop FF via an OR circuit OR.
This is done by applying a reset pulse to the IJ set terminal R of FF1, FF2, . . . .

In the figure, 01, 02... are output terminals, and in an electronic musical instrument, the output pulses generated at the output terminals 01, 02... are used to open and close the sound source signal, or The output pulse can be used as a control pulse for other circuits to control the circuit, or a signal can be applied directly to the Q terminal of the flip-flop, and the change in output impedance can be used to control the sound source. It is well known that signals are opened and closed.

The conventional priority selection storage circuit shown in FIG. 1 described above has the drawback that a transfer switch with a complicated configuration is required as a switch used in the circuit, which increases the cost of the device. Therefore, a differential circuit that includes a coil or a capacitor as a part of its constituent elements is required, making it impossible to integrate it into an integrated circuit.

The above-mentioned drawbacks of the first diagram are that the switches K1a, K2a, . This problem can be solved by a conventional circuit as shown in the block diagram shown in FIG.

That is, in Fig. 2, K1a, K2a...
・etc. are simple configuration switches having a movable contact and one fixed contact, and each switch is connected to a priority circuit A composed of an electronic circuit, and this priority circuit A
A set input is given to each memory circuit FF1, FF2, etc., each consisting of a flip-flop, and the reset operation for each memory circuit is performed by an electronic circuit provided on the output side of each memory circuit. Since this is done by the logic circuit B, the switch can have a simple configuration, and the circuit can also be integrated, so from this point of view, the second
Although it can be said that the conventional example shown in the figure eliminates the various drawbacks of the conventional example shown in the first figure described above, the conventional example shown in the second figure, however, has a priority circuit A.
Since the logic circuit B for the set operation is provided separately on the input side and output side of the memory circuit, this circuit is not suitable for integration into an IC, and also requires an increase in the number of switches. As a result, when attempting to expand the circuit, there are drawbacks such as the need for extra matrix circuits and logic circuits, or the complexity of the circuit configuration, and improvements have been desired. The present invention stores the set input and produces a logic 1 output at the output terminal Q when a logic 1 input is applied to the set terminal S, and when a logic 1 input is applied to the reset terminal R. and is configured such that when a logic 1 input is simultaneously applied to both the reset terminal R and the set terminal S, the memory contents are erased and a logic 0 output is produced at the output terminal Q. The memory circuit is connected to a plurality of switches K1, K2, etc. provided in the electronic musical instrument.
- provided for each individual switch, and a switch corresponding to the memory circuit is connected to the set terminal S of the memory circuit,
Further, with respect to the reset terminal R of the memory circuit, the output of the switch connected to the set terminal S of the memory circuit is in a logic 0 state and is connected to the set terminal S of the memory circuit. When a switch output of logic 1 is output from any other switch other than the switch, and even if the output of the switch connected to the set terminal S of the memory circuit is logic 1, that switch When a logic 1 switch output is output from any one of the switches with a higher priority than , a logic 1 input is given and the switch output of the switch connected to the set terminal S of the memory circuit is In the case of logic 1, and when the switch outputs of all switches with higher priority than that switch are logic 0, if the switch output of the switch with lower priority than that switch is logic 1, An electronic musical instrument is provided with a circuit layout formed by connecting logic circuits that can give a logic 0 input, and the circuit layout described above is divided into a plurality of groups, and each divided group has connection terminals each having two terminals. The present invention provides an electronic musical instrument equipped with a circuit arrangement configured to be connected in cascade one after another, thereby eliminating the various drawbacks of the above-mentioned conventional examples. I will explain in detail.

FIG. 3 is a block diagram of the main parts of the electronic musical instrument of the present invention. In FIG. 3, K1, K2... are switches provided inside the electronic musical instrument, and these switches K1, K2...
2... may be, for example, a switch connected to a foot keyboard.

Further, M1, M2, . . . are memory circuits, and these memory circuits M1, M2, . …
For each set terminal, reset terminal, Q output terminal, Q output terminal, etc., the same subscripts as 1, 2, etc. in the drawing code for each memory circuit are attached, but each memory circuit The set terminal at
When describing reset terminals, output terminals, etc. without distinguishing them, the subscripts are omitted and they are written as set terminal S, reset terminal R, etc. In addition, an input of logic 1 (high level state for positive logic, low level state for negative logic) is applied to the switch K and memory circuit M in the same way. When a logic 1 input is applied to the reset terminal R, it memorizes the set input and produces a logic 1 output at the output terminal Q, and for both the reset terminal R and the set terminal S. When a logic 1 input is applied at the same time, the memory contents are erased and a logic 0 (low level state for positive logic, high level state for negative logic) is output to the output terminal Q. FIG. 4 shows an example structure of a memory circuit having the above-mentioned characteristics. The memory circuit M shown in FIG. 4 is a special flip-flop composed of transistors X1, x2 and resistors rl to r6.
With respect to the state of , the states of Q output and Q output are as shown in Table 1.

That is, in the flip-flop shown in FIG. 4, when the set terminal S is logic 1, the Q output becomes logic 1, and when the reset terminal R is logic 1, and when both the set terminal S and set terminal R are logic 1, { , rQ can be used as a memory circuit M having characteristics such that the outputs are logic 0. (1st
Table) In FIG. 3, the switch KI is connected to the set terminal SI of the memory circuit MI, and the switch K2 is connected to the set terminal SI of the memory circuit MI.
The set terminal S of each memory circuit M is connected to the switch K to which each memory circuit M is attached.

Part 1, Part 2... are switches K1, K2...
A conductor that is individually connected to
indicates a conductor connected to a switch (or switch group) with a lower priority than switch KI shown in Fig. 3, and When there is a switch (or switch group) with a higher priority than the switch K4 shown in FIG. 3, a conducting wire connected to the switch (or switch group) with a higher priority is shown. Each switch K1,
The configuration of the circuit arrangement attached to switch K2... differs depending on the priority order of each switch relative to other switches, so let's take the circuit attached to switch K2 as an example. Explore the layout and explain the mechanism of its circuit configuration.

A set terminal S2 in a memory circuit M2 attached to the switch K2 is connected to the switch K2 and the conductor 2, and is connected to an AND circuit AND2 (hereinafter referred to as AND circuit 2) via an inverter V2.

Note that similar expressions are used for other logic bond circuits.)
is connected to one input terminal. The above AND circuit 2
An OR circuit OR2' which obtains the logical sum of the conductors L and 1 is connected to the other input terminal of the switch K2 so that switch outputs from all switches having a lower priority than the switch K2 are given.
The output side of a is connected. In addition, the memory circuit M2 described above
The reset terminal R2 of the switch K2 is configured to receive the OR output of the output from the AND circuit 2 and the switch outputs from all the switches having higher priority than the switch K2. , an OR circuit OR2b is connected to the reset terminal R2.

That is, in the illustrated example, the output from the OR circuit OR2C to which the conductors 〆3, 4, and 3, which are given the output from the switch with higher priority than the switch K2, are connected to the input side is the output from the AND circuit 2. OR circuit O input with output
The output side of R2b is connected to the reset terminal R2. In this illustrated example, it is shown as having an OR circuit OR2b and an OR circuit ○R2c.
In implementation, the input to the OR circuit OR2c may be directly provided as an input to the OR circuit OR2b, and the OR circuit OR2c may be omitted (this also applies to the OR3c). The structure of the circuit arrangement attached to switches K1, K3, and K4 is also similar to the structure of the circuit arrangement attached to switch K2 described above in relation to the priority between the switch and other switches. , a detailed explanation of the configuration of the circuit arrangement attached to each switch will be omitted. Next, the operation of the circuit arrangement shown in FIG. 3 will be described.

[1} When switch K2 is in the off state, switch K2
When the switch KI, which has a lower priority than the switch K2, is turned on, and all the switches whose priority is higher than the switch K2 are turned off.

At this time, when the switch KI is turned on, the conductor No. 1 becomes a logic 1 state (hereinafter referred to as logic 1), and the other conductors So2 to So4, SoL, and Sou are all in a logic 0 state.
(written as logical 0).

Since the output of the switch KI is set to logic 1, a set input is applied to the set terminal SI of the memory circuit MI. In this state, the output of the inverter VI given as one input of the AND circuit 1 is logic 0, and the other input of the AND circuit 1 is also logic 0, so the output of the AND circuit 1 is logic 0. Furthermore, since everything except the conductor Ku is at logic 0, the output of the OR circuit OR2C becomes logic 0, and therefore the output of the OR circuit OR2b also becomes logic 0, and the set input is stored in the memory circuit MI. switch KI
The logic 1 state of conductor 1 due to the on of switch KI
The outputs of the OR circuits PR2a, OR3a, and OR4a attached to all the switches K2 to K4, respectively, which have a higher priority than the above, are input as logic 1 to each of the AND circuits 2 to 4.

At this time, the outputs from the inverters V2-4 given to the AND circuits 2-4 are the same as those from all the inverters V2-4 because the inputs to the inverters V2-4 are all logic 0. The output is a logical 1, so
All logic 1 reset inputs are given to the reset terminals R2 to R4 of all the other memory circuits M2 to M4 except for the memory circuit MI, and the memory circuits M2 to M4 are reset and their respective memory contents are erased. Ru. ■ Switch K2
When the switch K3, which has a higher priority than the switch K2, is turned on while the switch K2 is in the off state.

At this time, only the conductor 3 becomes logic 1 due to the switch K3 being turned on.

Set terminal S of memory circuit M3 by turning on switch K3
The storage operation of the memory circuit M3 by applying a set input of logic 1 to the set of 3 and applying a logic 0 input to the reset terminal R3 is the same as the operation of the memory circuit MI in the above-mentioned section ``1''. Furthermore, since the reset operation of the memory circuit M4 attached to the switch K4, which has a higher priority than the switch K3, is the same as the set operation described in section {1} above, a detailed explanation of these operations will be provided. is omitted. Switch K2 has lower priority than switch K3
, KI, the logic 1 of the conductor 3 is applied to the reset terminals R2, RI of the respective memory circuits M2, MI via the OR circuit OR2c→OR2b and the OR circuit PR1c→OR1b, respectively. Reset.
'3} When switch K2 and switch KI are on at the same time, and all switches with higher priority than switch K2 are off.

At this time, the conductive wires Ku and 2 become logic 1 at the same time.

When the switch K2 is turned on, the set terminal S of the memory circuit M2 is turned on.
A logic 1 input is applied to the memory circuit MI, and a logic 1 input is also applied to the set terminal SI of the memory circuit MI by turning on the switch KI. First, in the circuit arrangement attached to switch K2, the output of AND circuit 2 is logic 0,
Furthermore, since the output of the OR circuit OR2c is also a logic 0, a logic 0 is given to the reset terminal R2 from the OR circuit OR2c, so the memory circuit M2 stores the set input of logic 1 given to the set terminal S2. .

On the other hand, in the circuit arrangement attached to switch KI, which has a lower priority than switch K2, the output of band circuit 1 is logic 0, but the logic 1 of conductor No. 2 is OR circuit ORIc→
Since it is applied to the reset terminal RI of the memory circuit MI through the OR circuit OR1b, both the set terminal SI and the IJ set terminal RI of the memory circuit MI become logic 1, the output state Q becomes the logic 0 state, and the set terminal SI Set inputs to are never remembered.

As described above, in the present invention, the performance can be improved by using a memory circuit with a special configuration in which the reset state is achieved when a logic 1 input is simultaneously applied to both the set terminal S and the set terminal R. A priority selection circuit with excellent characteristics and suitable for IC implementation can be easily constructed.

Next, a circuit arrangement with a large number of switches can be easily constructed according to the construction principle explained in the circuit arrangement shown in the third diagram above. 1 I with pin number
If the IC package can be accommodated in a C package and the number of IC packages can be increased according to the number of switches required, electronic musical instruments of any size can be freely used in standard packages. This is highly desirable because it can be configured as follows.

Figure 5 shows that when the circuit layout shown in Figure 3 is divided into multiple groups from the above perspective, the circuit layouts accommodated in each group can be easily connected vertically. FIG. 2 is a block diagram illustrating the principle of configuration of a circuit arrangement to enable this.

In FIG. 5, frames Wa and
The circuit layout in Wb and Wc has a configuration in which an OR circuit OR〆co and an OR circuit ORuco are newly added to the circuit layout attached to each switch K as already described with reference to FIG. , each constitute a group of circuit layouts, and the circuit layouts of each group Wa, Wb, Wc may be housed in separate IC packages. and,
When connecting each group of circuit arrangements in cascade one after another, terminals Uci and Lco in one group, for example, the circuit arrangement of Wb, are connected to the terminals Uci and Lco of the circuit arrangement of one group, for example, of the circuit arrangement of WC, which belongs to a switch group with a higher priority. Terminals Uco and L
cj, and also connect the terminals Uco and Lci in the circuit arrangement of one group, e.g., Wb, to the terminals Uci and Lco in the circuit arrangement of the - group, e.g., Wa, belonging to a switch group with a lower priority than that group. By simply applying this simple method, any circuit with a large number of switches can be easily configured, and there is no need for a matrix circuit or the like for coupling the circuit arrangements of each group.

It will be readily understood without explanation that the circuit arrangement corresponding to the many switches vertically connected by the above means operates exactly the same as the circuit arrangement described with reference to FIG. Will.

In addition, in the figure, Mn, Mn11..., Mm
etc. are memory circuits, Km..., Kn, Kn11...
. . . are switches, ○m, 0m, 0m+1, etc. are output terminals. Also, in order to simplify the illustration, group W
Some of the AND circuits and OR circuits in a and Wc are not given drawing symbols. In this way, in the present invention, for each group obtained by dividing into a plurality of groups, the outputs of the switches belonging to the group and the outputs from the switch groups having lower priority than the switches belonging to the group are logically divided. An OR circuit OR soco that outputs the sum, and an OR circuit ORuco that outputs the logical sum of the output of the switch belonging to the group and the output from the switch group having a higher priority than the switch belonging to the group are provided. In addition, a terminal Lco connected to the output side of the OR circuit OR〆cc and a terminal Uco connected to the output side of the OR circuit ORuco,
In addition, by simply providing a terminal Uci that receives switch outputs from a switch group with a high priority and a terminal ratio i that receives switch outputs from a switch group with a low priority, the scale can be expanded extremely easily as described above. This results in a circuit layout that is possible.

As is clear from the detailed explanation above, in the present invention, by using a special memory circuit, a priority selection circuit can be constructed only from the set terminal S and the IJ set state R side, so it is easy to integrate it into an IC. In addition, even when the circuit layout is divided into multiple groups so that the number of circuits can be accommodated in an IC package having a standard number of pins, each group can be connected extremely easily. , it has various advantages such as the ability to easily obtain circuit layouts of any size by simply connecting a group of standardized circuit layouts one after another according to the number of switches required. An electronic musical instrument can be obtained very easily.

[Brief explanation of the drawing]

1 and 2 are block diagrams of different configurations of a conventional priority selection circuit, FIGS. 3 and 5 are block diagrams of different embodiments of the present invention, and FIG. 4 is a block diagram of a storage circuit. It is a circuit diagram of an example. K1t~K3t..., K1a~K2a..., KI~K4
...Switch, FFI to FF3...Flip-flop,
A: Priority circuit, B: Logic circuit, D
I~D3... Differential circuit, 01~04...
・Output terminal, M, MI to M4, Mn, Mm...
Memory circuit, OR, OR1b, OR1c. OR2a~OR
2c, OR3a~OR3c, OR4a, OR4b, OR
Mo, OR〆co・・・OR circuit, ANDI~A
ND4...AND circuit, m... Close contact, b...
Flake contacts. Younger brother's drawing bag 2 drawing 3 drawing tam drawing iron

Claims (1)

[Claims] 1 When a logic 1 input is applied to the set terminal S,
It memorizes the set input to produce a logic 1 output at output terminal Q, and simultaneously when a logic 1 input is applied to reset terminal R and for both reset terminal R and set terminal S. A memory circuit configured to erase the memory contents and produce a logic 0 output at the output terminal Q when a logic 1 input is applied to each of the plurality of switches provided in the electronic musical instrument. A switch is attached to each switch, and the set terminal of each memory circuit is connected to the switch to which the memory circuit is attached, and the output of the switch is provided as one input of the AND circuit via an inverter. Further, as the other input of the AND circuit, the OR output of the output of a switch having a lower priority than the switch to which this AND circuit belongs is given, and further, the output of the AND circuit and An electronic musical instrument having a circuit arrangement in which an OR output with the output of a switch having a higher priority than the switch to which this AND circuit belongs is given to a reset terminal in a memory circuit attached to a switch to which said AND circuit belongs. . 2 When a logic 1 input is applied to the set terminal S,
It memorizes the reset input to produce a logic 1 output at output terminal Q, and simultaneously stores the reset terminal R and set terminal S when a logic 1 input is applied to reset terminal R. A memory circuit configured to erase the memory contents and produce a logic 0 output at the output terminal Q when a logic 1 input is applied to each of the plurality of switches provided in the electronic musical instrument. The set terminal of each memory circuit is connected to the switch to which the memory circuit is attached, and the output of the switch is provided as one input of the AND circuit via an inverter. In addition, as the other input of the AND circuit, the OR output of the outputs of the switches having a lower priority than the switch to which this AND circuit belongs is given, and furthermore, the output of the AND circuit and , a circuit arrangement in which the OR output with the output of a switch having a higher priority than the switch to which this AND circuit belongs is given to the reset terminal of the memory circuit attached to the switch to which the AND circuit belongs, respectively. is divided into a plurality of groups containing an appropriate number of switches and corresponding auxiliary circuits, and each of the individual groups obtained by said division is given the output of each switch belonging to said individual group. a first disjunction means for obtaining a disjunction between the disjunction output and the disjunction output of the output of each switch belonging to a group having a switch having a higher priority than the switch belonging to the group, and each switch belonging to the group; and a second logical sum means for obtaining a logical sum of the logical sum output of the output of the switch and the logical sum output of the output of each switch belonging to the group having a switch having a lower priority than the switch belonging to the group. An electronic musical instrument with a circuit layout.