JPS603041A - Memory selection control system - Google Patents

Abstract

PURPOSE:To eliminate an unusable memory area without improving the quality of a program by varying the correspondence between a memory address supplied from a central processing unit and a memory element. CONSTITUTION:This memory selection control system is constituted including an address decoder 7, mode address register selective writing circuit 8, mode address register groups 9 and 10, mode address selecting circuit group 11, memory selection register group 12, and selective detecting circuit group 13. Then, a memory selection signal is outputted according to an address decoding signal from the address decoder 7 and a memory selection address signal from the memory selection register group 12.

Description

[Detailed Description of the Invention] [Technical field to which the invention pertains] The present invention relates to a memory selection system, in particular, an information processing system that is composed of a central processing unit, a memory device, and peripheral devices. The present invention relates to a memory selection control method for selecting a memory in a computer.

[Prior art]

The conventional memory selection control method simply decodes the memory address given by the central processing unit &+ and outputs a memory selection signal to the corresponding memory. In other words, the correspondence between memory addresses and memory elements is fixed.

Therefore, the system may become inoperable when a memory area in use becomes unusable due to a fixed fault, or the system becomes unusable when a failure occurs in a memory area in use.

To avoid this, create a program that avoids unusable memory areas and uses memory once! 7.Central processing units were required to develop advanced programs that could be modified or changed program storage areas and data storage areas by themselves from the beginning.

Furthermore, recently - microprocessors I and S
Some types of I have a dedicated memory area specific to the processor, and when a central processing unit-j containing multiple such microprocessor LSIs tries to access the memory of the main storage device, the memory Such microprocessor LSI
'f: A central processing unit equipped with multiple units is not practical, and since the correspondence between memory addresses and memory elements is fixed, it is impossible to change the capacity of the memory element to one with an increased or decreased capacity. there were.

That is, the conventional memory selection system has the drawback that it is impossible to avoid unusable memory areas unless the program is sophisticated.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory selection control method that can avoid unusable memory areas without having to assimilate a program.

That is, an object of the present invention is to provide a memory selection control unit in the main device (:t:i device) with a mode address register group and a memory selection check circuit, By using the decoded comparison data in Ura-Sho 5, it becomes possible to make the correspondence between the memory address given by the central processing unit and the memory element variable instead of identifying it, and furthermore, by creating a plurality of mode address register groups, these registers II- A memory element comprising a mode address selection (b) path for selecting a mode address register group, which selects and uses the mode address register group according to a mode address register selection signal and can be used instead of the mode address register group; Memory selection fltll Q1j that can control memory selection according to the capacity of
The goal is to provide a method.

[114th feature of the invention] The memory selection control method of the present invention selects a mode address register selection signal consisting of a plurality of bits given from a central processing unit, when a mode address register 1 strobe signal is supplied. a mode address register selection circuit that outputs an input signal;
a plurality of mode address registers that output a -t insert mode address signal when the mode address register insert signal is supplied with a decode comparison data signal consisting of a plurality of bits given from the central processing unit; and the mode address register. No. 16 k tFf Mode selection of 1 or more bits of n given from the central processing unit 'la' selection mode address 1 'i k Multiple mode address selection 6 times R5 and 1ull notation A plurality of memory selection registers for outputting a memory selection address lever, which inputs a selection mode address signal by a memory selection register store stroke No. 1 which is inputted directly from the central processing unit 3, and from the medium heat processing device 61. An address decoder that manually inputs a memoriato 1/s signal consisting of a given number and node and outputs an address lever toy No. 6, and an address decoder that outputs an address lever toy No. 6, which is selected by comparing the memory selection address lever and the address decode signal with the bit mother. and a plurality of selection detection circuits that detect the memory selection and output a memory selection signal.

That is, the memory selection control method of the present invention is such that, in an information processing system constructed of a central processing unit, a main storage device, and a plurality of peripheral devices, the memory selection control section in the main storage logic is controlled from the central processing unit. A mode address register selection write circuit receives a mode address register selection signal and a mode address register input nutrobe signal consisting of a plurality of bits as input, and outputs a plurality of mode address register input signals; The decode comparison data signal consisting of several bits is set to 1 by the output signal of the mode address register selection circuit.
a plurality of mode address select circuits that select the output signals of the plurality of mode address registers according to a mode selection signal of one or more bits given from a central processing unit; 2i, the number of modes to be recorded; It is equipped with a plurality of memory y'lA selection registers into which the output signal of the address selection circuit is written using the memo IJJ selection register blue strobe code given from the central processing unit, and further includes a plurality of memory y'lA selection registers in which the output signal of the address selection circuit is written in by the memory IJJ selection register blue-knit strobe code given from the central processing unit. an address decoder that inputs a memory address signal consisting of a memory address signal and outputs an address decode signal; It is composed of a plurality of circuits that make up the Tm circuit.

As a result, the correspondence between the memory address given by the central processing unit and the memory element 1M.
<Can be made into J-hen, and even more so 2 Tsukuda meet i3t
- memory address of h ri, 'j' lc - biological parent,
Therefore, it is possible to easily avoid the unusable area without relying on changing the program of the central processing unit. To avoid collisions, memory selection is controlled according to the capacity of the memoria child.

[Explanation of Examples]

Next, the fruit of the present invention is 11 songs per 11 minutes; 1. , will be explained in detail.

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
FIG. 6 is a detailed circuit diagram of each circuit shown in FIG. 1.

The 1' memory selection control system shown in Figure 2iI41 includes an address decoder 7, a mode address register quick selection layered circuit, a mode address register 11.9.10, a mode address selection circuit group 11, and a memory selection register 1n12.
and a selection detection circuit phase, 1: at the back.

Here, the mode address register group 9 is composed of mode address registers 14 to 17, and the mode address register group 10 is composed of mode address registers 18 to 21 (441).
The mode address selection circuit set 11 is set to 1 in mode address selection times 22 to 25, the memory selection registers hi' and 12 are set to n4 in memory selection registers 2b to 29, and the f selection detection circuit is set to n4. Coarse: 13 is selection detection circuit 30
~33 Lc: li & some awn.

In other words, the 1' memory selection control force formula shown in FIG. S.L. -8L
2. CLK and outputs eight mode address register bit signals 38 to 45.
A mode address register selection detection circuit 8 to output and a 4-bit code ratio data m'j 2 ri input from the central processing unit j.

Input terminal. - D3 and the output of the mode address register copy selection informing circuit 8 supplied to each clock driver C is determined by The eight mode address registers 1/disk 14-2] are divided into two groups, and one mode address 1/disk register 11-2 is divided into two groups.
The mode address signal 47, which is the output signal of the mode address register group 10, is sent to each input terminal 5Ao, and the mode address signal 48, which is the output signal of the other mode address register group 10, is sent to each input terminal 5Ao. j: each input terminal S
, r36-8133 from the central office,
These mode address signals 47 . = 1.8 and outputs it to the output terminal S Do-8D8 as a long selection mode at L/sui 1j-I'i'49; Each of the selection mode address signals 49, which are output signals of the mode address selection circuits 22 to 25, is supplied to each input terminal 1) o-D, and the memory selection considered from the central processing unit supplied to each clock terminal C is performed. Four memory selection registers 26 to 2 to which writing is performed by register write strobe signal 6
9 and a memory address signal 1 consisting of 2 bits inputted from the central processing unit to input terminal A. , A1, and 4
An address decode signal 46 consisting of bits is output from terminal A.
Do-AD.

an address decoder 7 that outputs an address decoder 7, and an address decode signal 46, which is an output signal of the address decoder 7, is supplied to each input terminal CAo-CA, and a memory selection signal that is an output signal of the four memory selection registers 26 to 29 is supplied to each input terminal CAo-CA. Address signals 50 to 53 are input to each input terminal CBo.
-CBll and outputs four memory selection signals 34 to 37 to respective output terminals SC.

Next, the operations of each of the routes shown in FIGS. 2 to 6 will be explained with reference to the first page.

FIG. 2 is a circuit diagram showing an example of the address decoder 7 shown in FIG. 1, and the input block A is shown in FIG. , A1, and output address decode signals 46 to four output terminals ADO-AD, respectively.
Output.

FIG. 3 is a circuit diagram showing an example of the mode address register selection write circuit 8 shown in FIG. 1, and includes three input terminals 8Lo,
A decoder that supplies input signals to SL, SL2 and outputs eight decoded signals (a) to (h)]01 and the decoded signals (2) to (h) from the decoder 101 to one input terminal. It is composed of eight two-man gates 102 to 109, which supply a strobe signal 17 to the input terminal CLK, and a strobe signal 4 including a mode address register to the other input terminal CLK.
9 outputs mode address register 1 included signals 38 to 45 from output terminals CLo to CL7, respectively. As is clear from the operation timing shown in FIG.
Decoder 101 among people and guts 102 to 109
The AND condition of the decode signal (al~(hl) from the mode address register gift strobe signal 4 is
Only the gate you put out will be in the exit state.

Figure 4 shows the eight mode address registers 1 shown in Figure 1.
4 to 21 and four memory selection registers 26 to 290, a circuit diagram showing one example of a total of 12 registers. -113 clock input terminals C supplied to each clock input terminal C. This is because, as is clear from the operation timing shown in FIG. 8, the four input signals supplied to the input terminal DO" , output terminal 1) To-DT.

@Figure 5 shows the four mode address selection circuits 2 shown in Figure 1.
Input terminal 5Ao is a circuit diagram showing one example of Nos. 2 to 25.
-8As, each of the four input signals is supplied to one input terminal trap, and the other input terminal SLT is supplied with the memory selection register write strobe signal 6.
Each of the four input signals supplied to human coupled gates 115, 117, 119, 121 and input terminals SBo to 5BsVC is supplied to one input terminal, and the memory selection register ■ strobe input is supplied to the other human input terminal. A signal whose polarity is inverted from H No. 6 by an inverter 114 is connected to the four two-large canand gates 116, 118, 120, 122.
．． ! : Previously mentioned two power Nando game 115 and 6'I n+'
: Two large Canand gates 123 that supply each output signal of the two large Canand gates 116 to their respective input terminals, and a two-man powered NAND gate 119, 120 that similarly supplies each output signal of the two-man powered NAND gates 117, 118. 2-man power gate 25. 2-man power gate 121.122 which supplies each output signal of
It is composed of two large canand gates 126 that supply each output signal. As is clear from the operation timing shown in FIG. 9, when the signal supplied to the input terminal SLT is in the on state (1), K
15,11”/.

119 and 121 are operating effectively, and each output terminal 5Do-8D of the four two-man NAND gates 123-126.

A mode address signal 47 is output to. Furthermore, when the 1εI signal supplied to the input terminal SLT is in the off state (0), the four two-person canand games) 116, 118°
20.122 is operating effectively, and each output terminal 5Do-8D of the four two-person NAND gates 123-126.

A mode address signal 48 is output to.

FIG. 6--Four selection detection circuits 30 to 33 shown in FIG.
This is a circuit diagram showing one example of input terminals CA, -CA.
Each of the four addressing code signals 46, which are supplied to 3 and 6, is supplied to one input terminal CBo-CB.
Four two-player canando games 1-1 that supply the four memory address selection signals 50 supplied to s to the other input terminal.
27-130 and these four 2-person Kanandgut 127
It is composed of a four-manpower NAND gate 131 in which each of the output signals of 130 to 130 is connected to four input terminals, respectively.

As is clear from the operation timing shown in FIG.
The memory selection signal 34 is outputted from the output terminal SC of the four-manpower NAND gate 131 only when there is one of the two-manpower NAND gates 127 to 130 in which both of its two input terminals are in the ON state (1). Tsum input terminal CAo
and CBo, CA, and C10.

CA2 and CB2. When both CA8 and CB are in the ON state (1), the output terminal SC of the 4-man powered NAND game 131 becomes the ON state LMLII.

Next, with reference to FIGS. 1 and 11, assuming the operation of each part explained above, the memory address given by the medium heat processing apparatus (which is the first object of the present invention) (in FIG. 1) will be explained. The correspondence between the memory address signal 1 (which corresponds to 2 bits to /7) and the memory element (which corresponds to the four memory selection signals 34 to 37 in Figure 1) is not 16J constant.
i'" Explain what you can do to make it weird.

In the operation timing shown in FIG. 11, the numbers in the timing are 2 bits (AO, A, l), 3 bits, and (SLo
-8L, ), 4bi, h (Do-,1)3. DT.

-1) T.

CBo-CB, CAo-CA,), each part 1 (the state of the bow is expressed in hexadecimal).

Therefore, for signals consisting of 2 and 3 bits, 16
It is best to focus only on the lower 2 bits and lower 3 bits of the base number.

34 in the operation timing shown in Figure 11.
The numbers shown in the timings of `` `` 35 '' `` 36 '' `` 37'' are the 2 at each point in time.
The hexadecimal representation of the state of memory address signal 1 consisting of bits is associated with ``switch memory correspondence''.
On the left and right sides of the line 1, there is a 2-bit memory address signal 1 and four memory selection signals 34 to 3.
It can be seen that the correspondence of 7 is different. Tsukiri' 34
” may be output when ``1'' is 018, or may not be output, and ``35'' may be output when °'l'' is 116, or may be output when ote. There are cases where "36" is output at the position of "1" at 216, and there are cases where it is output at the position at the position of 1,6.
37'' is not output when '°1n is 2.6, and there are cases where jfJ is output.

In the end, when the memory selection register cutting strobe signal 6 rises for the second time (``switch memory correspondence''), 2
The correspondence between the memory address signal 1 consisting of bits and the four memory selection signals 34 to 37 is different.

In the mode address register 14, l:'f, 3 pins)・
When the mode address register 14 is selected by the mode address register side selection signal 3 consisting of the mode address register side selection signal 3 and the mode address register write strobe 1b 4, the decoding ratio soft data newsletter 2 consisting of 4 bits is written into the beak and output. It is output to terminal DTo-1)T.

Similarly, the remaining three mode address registers 15 to 17
Also, the decoding ratio consists of 4 bits (tanata signal 2 is 7
; input, each output path 1 child 1) T. ~ Output to DTR.

14'' to t+ in the operation timing shown in FIG.
17 n initial (Iu 81.6p 4167216+
'JI6 tlcL each next write data OI6+
816 + 416 y 2□6 has already been written in the same procedure as when it was inserted into the air.

The polarities of the output signals of the four mode address registers 14-17 selected by the four mode address selection circuits 22-25 are applied to the input terminals of each of the four memory selection registers 26-29.

Memory selection register)'-, 1. When the input strobe signal 6 is high, the states of these input terminals are written into each memory selection register 26-29, and the output terminals of each
t) T, -DT, output to four selection detection circuits 3
It is applied to each input terminal CAo-CA3 of 0 to 33.

As is clear from the operation timing shown in FIG.
The states of B, whose initial values were all O'16, changed to 816 + '! at the rising edge of the first memory selection register write strobe signal 6, respectively. tel 216 +01
6, and then at the rising edge of the second memory selection register 1 strobe signal 6, respectively 016°816+4
It changes to 16 + 216.

On the other hand, an address decode signal 46, which is an output signal obtained by decoding the 2-bit memory address signal 1 by the address decoder 7, is applied to input terminals CAo-CAs of each of the four selection detection circuits 30-33. In the four selection detection circuits 30 to 33, the input signals to the input terminals CAo-CA and the input signals to the input terminals CBo-CBs are compared bit by bit, and when a selection condition is detected, each output terminal SC is turned on. It becomes state (1).

Next, the ability to realize different address spaces, which is the second object of the present invention, will be explained with reference to FIGS. 1, 11, and 12.

In the operation timing shown in FIG. 12, the numbers in the timing are 2 bits (Ao, Al) and 4 bits (DT
o-DT, 5Do-8D, , CBo-CB, .

The status of each (ilIi) consisting of CAo-CA3) is shown in hexadecimal.

Therefore, for a signal consisting of 2 bits, it is better to pay attention to only the lower 2 bits of the hexadecimal number. Furthermore, during the operation timing shown in FIG.
” The numbers shown in the timing indicate the state of memory address signal 1 consisting of 2 bits at each point in time.
Corresponding to the book expressed in digits, in the ``address space switching section'', the memory address signal 1 consisting of 2 bits is
It can be seen that the correspondence between the four memory selection signals 34 to 37 is different from that in other sections. Tsum p ” 34”
1'' is output as 1.6 only in the pad address space switching section, and 1# is output as 0 and 6 in other sections.

Similarly, °゛37'' is ``1'' only in the ``address switching section''.
" is output as 016, and in other sections, Pa1" is output as 31.
11 is output. Also, "35" means "1" is 11. in "address switching section". However, in other sections, "1" is output as 116. Similarly” 36
"1" is not output even though it is 2 in the address switching section, and the pulse # is output at 218 in other sections.

In the end, after the mode selection signal 5 is in the off state (0) and the memory selection register write strobe signal 6 rises, the mode selection signal 5 becomes in the on state (1), and the memory selection register write strobe signal 6 During the "address space switching interval" until the rise of the address space, the address space is different from other intervals.

The operation timing shown in FIG. 12 is as follows.
ite l 216'+ 116 r'its l
216 + 1111-816, but these initial values are already written in the mode address registers 14 to 21 according to the method of writing mode address registers 14 to 17 shown in FIG. be.

When the mode selection signal 5 is in the on state (1), the four mode address selection circuits 22 to 25 are assigned to each SA.

~SA3 manual power is selected and these input terminals SA0~SA.

The polarity of the input signal supplied to each output terminal 5D
output to o-8D. Furthermore, when the mode selection signal 5 is in the off state (0), the four mode address selection circuits 2
2 to 25 are respective input terminals SB0 to SB.

The polarities of the input signals supplied to these input terminals SB0 to SB are outputted to the respective output terminals SD and -8D3.

Each time the memory selection register write strobe signal 6 rises, the states of the output terminals 5Do to 8D of the four mode address selection circuits 22 to 25 are written to the four memory selection registers 26 to 29, respectively. , the output terminals DT0 to D of each of these four memory selection registers 26 to 29
T, and applied to input terminals CB0 to CB3 of four selection detection circuits ts3o to ts33, respectively. The subsequent operation is similar to that shown in FIG.

Next, with reference to FIGS. 1, 11, and 13, the third object of the present invention, which is the memory selection control corresponding to the memory element capacity ttK, will be fully explained.

In the operation timing shown in Fig. 13, the numbers in the timing are 2 pits t・(Ao, A1), 4 pits (DT0~DT□ CB0~CB,, CA0~CA,
) The status of each signal is shown in hexadecimal.

Therefore, for a signal consisting of 2 bits, it is better to pay attention to only the lower 2 bits of the hexadecimal number.

Furthermore, "'34" in the operation timing of Fig. 13
The numbers shown during the timings of "35", "36", and "37" correspond to the hexadecimal representation of the state of the memory address signal 1 consisting of 2 bits at each point in time. Comparing with the operation timing shown in Figure 11, the decoding ratio soft data No. 46 2 consisting of 14 bits for "14" to "17" is 1.
The written contents are different.

In the operation timing shown in FIG. 11, 816+41L21
The decoded comparison data 4 of the 4 buckets of 6 + 0Ill r is written in, but at the operation timing shown in FIG. The value is 1 IiI @ including 1
It is.

As a result, the operation timing shown in FIG.
0" CB0~Cl38. "31" Cklo-
When comparing CB and CAo-CA of '30 to 33'' bit by bit, the AND condition can always be detected for only one bit, but at the operation timing shown in Fig. 13, '30'' is detected.
``CB, 〜CB, , ``31'' CBo-CB
A 2-bit AND condition is detected by comparing CA and -CA of 3 and 30 to 33'' bit by bit. In other words, ``revert the memory correspondence'' during the operation timing shown in FIG. 11. If you pay attention to the left side of the line, in this case, ``1'' is outputted to 34'' when it is 0.6, and ``1'' is outputted to 35'' when it is 116. At the operation timing shown, lci "1" at 34''
is output when OI is 1 and when it is 1.6, and t1 is output at 35'' and 2■, 3, and 6.

As a result, the operation timing shown in h1.131 of the memory element is different from the operation timing shown in FIG. corresponds to twice as many. However, the circuit operating in both FIGS. 11 and 13 is the one shown in FIG. 1, and by simply changing the contents of the decoding ratio soft data signal 2, a memory selection control operation corresponding to the capacity of the memory element can be executed. be done.

〔Effect of the invention〕

The present memory selection control method uses memory selection signals by address decoding (by changing the selection detection circuit).
Instead of outputting only in response to No. 3, it can be output in response to the address decode signal and the memory selection address signal, so the correspondence between the memory address signal and the memory element can be made variable instead of being fixed. This has the effect of avoiding unusable memory areas without making the program more sophisticated.

That is, the memory selection system of the present invention is realized by making the correspondence between the memory address given by the medium heat processing device and the memory element variable instead of 111 constant, and switching to two or more different memory address spaces. Yes, 1
A large advantage is that memory selection can be controlled according to the capacity of the memory element connected to it.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of the address decoder shown in FIG. 1, and FIG. 3 is an example of the mode address register selection detection circuit shown in FIG. 1. 4 is a circuit diagram showing an example of the mode address register and memory selection register shown in FIG. 1; FIG. 5 is a detailed circuit diagram showing an example of the mode address selection circuit shown in FIG. 1; FIG. 6 is a detailed circuit diagram showing an example of the trace selection detection circuit shown in FIG. 1, and FIG. 7 is a detailed circuit diagram showing an example of the trace selection detection circuit shown in FIG. Fig. 8 is a timing chart for explaining the circuit operation of the mote address register and memory retreat disk shown in Fig. 4, Fig. 9 is a mode address register shown in Fig. U75, Figure 10 is an operation timing chart for explaining the circuit operation of the selection circuit. Good J production timing chart for
Figure 1, Ml Figure 2 and Figure 13C Laughter shown in Figure 1
This is an operation timing chart for clarifying the overall operation of the la example. l...Memory address signal, 2...Decode comparison data signal, 3...Mode address register selection signal, 4...Mode address register write strobe signal 5...Mode selection signal, 6...Memory selection register write strobe signal, 7...Address decoder, 8...
・Mode address register selection 1 circuit, 9,1.0・
...Mode address register group, 11...
Mode address selection circuit group, 12...Memory selection register group, 13...or selection detection times M%, 14
~21...Mode address register, 22~2
5...Mode address Shiba selection ship, 26-29.
...Memory selection register j130 to 33...
・Include selection detection circuit Pi)+, 34-37...Memory selection signal, 38-45...Mode address register entry No. 1A, 46...Address decode (
, i number, 47.48...Mode address signal,
49...Selected mote address signal, 50 to 53
...Memory selection address signal, 101...
...Decoder, 102-109...Two-man power gate, 110-113...Flip-flop, 114...Inverter, 115-130.
...2-man powered NAND gate, 131...4-man powered NAND gate, (a) to (h)...Decode signal, 5Lo-8
L2. CLK, Do-D3,5Ao-3A,. 5Bo-8B8. Ao,A,,CA,-CA,,CBo
~CB3,・−,,,input terminal, CLo-Cl3,5
Do-8JJ,. ADo-AD,, SC,I)T, ~I)Ts,,,
,,, Output terminal, C...1 clock input terminal. □□□- 1 substitute patent attorney Uchihara's Award ('112,-,
/97C)1ro /1in I Z/)t , E cod 3] S) nro Otsushi I Iθshi121.3121-1, shi /I/ - nυ,, <(('A=1) t'BP 111 1ρI I21 Mei /θ Figure 1 '3"Sbr, Sit"" η4 /l Figure 1/2'Dmu of Figure 4'~〃IJ -CCC-1\-\y 7,1
figure

Claims (1)

[Claims] A mode address register selection write circuit that outputs a plurality of mode address register convolution signals when a mode address register write strobe signal is supplied with a mode address register selection signal consisting of a mantissa bit given from a medium heat processing device i+i. Then, the code ratio data signal consisting of multiple bits given from the central processing unit itself is written to the write mode address (multiple modes that output M) when the 1-input signal is supplied. an address register, a plurality of mode address selection circuits that select the mode address signal using a mode selection signal of one or more pits given from the central processing unit and output a selected mode addressing signal; 1 by the memory selection register 1 strobe signal given from the central processing unit.
a plurality of memory selection registers that output write memory selection address signals; an address decoder that inputs a memory address signal consisting of a plurality of bits provided from the central processing unit and outputs an address decode code; The present invention may be characterized in that it includes a mantissa selection detection circuit that detects that the memory selection address converter and the address code H of item 1j are selected bit by bit and outputs a memory selection signal. Memory selection control method.